Many challenges face system designers as we head into 2010. But some of the most difficult are equally challenging for the EDA vendors who must provide the tools and methodologies to deal with them.
The burgeoning complexity of designs at process nodes from 45 nm and below portends a serious crisis in at least two significant areas: verification and software. These issues, and many more that are closely related including physical verification, keep EDA CTOs awake long into the night. Some pieces of the puzzle are already in place while others are brewing.
In general, designers are ramping up for doing more design work at higher levels of abstraction. “This is driven not only by rising complexity and cost, but also by the advent of technologies like 3D chip stacks, which rule out iteration in the back end,” says Mike Gianfagna, vice president of marketing at Atrenta.
So, says Gianfagna, power management, design verification, design for test, and timing closure will all be “close to done” before handoff to synthesis and place and route. This will make the traditional back end of IC design a more predictable, routine process, which in turn will hasten the back-end flow’s maturity, commoditization, and consolidation.
The overall cost of design is rising rapidly (Fig. 1a). Projections are for the cost of software design and debug to skyrocket. “As we move into 32 nm and below, which we’ll start to see in the next year and a half, the cost of design is a huge issue,” says Tom Borgstrom, director of solutions marketing at Synopsys. “Some projections show the cost for large designs on those nodes will approach $100 million. That affects fundamental economic decisions.”
SOFTWARE DESIGN A BURDEN
For an example of where this kind of complexity is leading, look no further than Intel Labs’ December announcement of a 48-core single-chip “cloud computer.” Fabricated on a 45-nm, high-k metal-gate process, this test chip consumes 25 W when in power conservation mode and just 125 W in full-bore performance mode, Intel says. While Intel has plans for a commercial release of six- and eight-core processors in 2010, the cloud-computer test chip could potentially scale up to 100 processors on a single die.
Such complexity places enormous burdens on the software-development side of the system house (Fig. 1b). Thus, EDA vendors have embedded software on their radar screens. “One of the biggest trends rising to the top is software,” says John Bruggeman, chief marketing officer at Cadence Design Systems.
Bruggeman sees Intel’s acquisition last summer of Wind River Systems as a “massive signal to the marketplace that the total value proposition that a chip company delivers to its end customers must include software.” Bruggeman also noted Cavium’s recent acquisition of embedded-Linux house MonteVista Software.
What this means to Bruggeman, Cadence, and the rest of the EDA community is that the problem set for designers is changing rapidly and dramatically. “It points toward the concept of hardware design for software,” says Bruggeman. “We have all talked about design for manufacturing and yield. You will see in years to come that those initiatives will pale relative to hardware design for software.”
Central to this concept is the ability to perform simultaneous design and verification of hardware and software. “It’s no longer enough to have an Eclipse-based toolset to debug software,” says Bruggeman, “because the problem is usually in the integration of hardware and software and not necessarily in the software itself.”
Speaking from his prior experience as chief marketing officer at Wind River Systems, Bruggeman sees a huge opportunity in this space for the EDA industry. “At Wind River, I knew this problem intimately and I knew that the solution set would come not from embedded software but from EDA. But not from EDA as we know it now, but EDA as it will be.”
CO-DESIGN GOING MAINSTREAM
These days, it’s common to see system-on-a-chip (SoC) development teams in which software designers outnumber hardware designers by a large margin. Software developers will increasingly turn to ways of getting an early start on their work.
Two approaches to watch in 2010 are virtual platforms (VPs) based on transaction-level models (TLMs) and FPGA-based rapid prototyping. VPs are, for the most part, SystemC TLM 2.0-based platforms that stitch together TLMs of major intellectual property (IP) blocks, whether from IP vendors or homegrown. With VPs, software teams can get busy up to 12 months before first silicon.