From a signal-integrity standpoint, it's interesting to consider that pc-board designers have long been dealing with issues that have just recently hit IC designers. Due to the relatively larger geometries of structures on boards, board designers have struggled with inductance and crosstalk for some time.
From the beginning stages of a board design, there are methods that designers can use to avoid signal-integrity problems downstream, especially if cost considerations dictate the use of tried-and-true FR-4 in high-end applications (see "Wringing More Performance From FR-4," p. 70). Careful floorplanning is one of them. Problems in this area can stem from having different people perform schematic capture and layout.
"Simulation and floorplanning is much more logically done by the person who does schematic capture than by the person who does layout," says Electronic Workbench's Wignall. "Often, that's the same person. But if not, it's the guy who enters the schematic who has a general idea about how the circuit functions electrically, whereas the pc-board designer is the guy who figures out whether to place an IC in the top left corner or the bottom right corner. He makes sure everything's there and connected and manufacturable but often does not understand how the circuit operates."
Ultimately, though, for a high-speed board, signal-integrity analysis comes into play. According to Cadence's Metcalfe, "Because of the geometries and frequencies we see on a pc board, we're moving more and more toward solving the complete Maxwell equations. And we're able to make fewer and fewer assumptions to simplify the problems."
It's no longer possible to analyze signal integrity solely in terms of board traces at gigahertz speeds. "Designers must look at the timing from die to die instead of from pin to pin," says Metcalfe. In the past, designers would have some timing budget for the interconnect from the pin to the die and treat that as part of the overall timing. But it would be a relatively unknown quantity compared to the board traces. Now, the approximations used to guesstimate what happens between the die and the board are falling apart.
On the board itself, signal speeds cause assumptions and approximations to fail, too. For instance, what happens to signal integrity when traces carrying a differential pair turns a corner? Designers must concern themselves with intra-pair signal skew for differential signals, and skew with respect to the clock for single-ended signals.
Structures like trace bends, microvias, and others complicate signal-integrity analysis because they're difficult to model accurately. Consultants like SiQual's Hinz rely on full-wave 3D field solvers for such tasks. Tools, including Ansoft's Spicelink with both 2D and 3D field solvers and a Spice simulator, fill the bill for such applications (Fig. 4). Spicelink, now available in Version 5.0, produces accurate 3D distributed models. It also includes an IBIS driver to run system simulations.
When designing transmission lines, for instance, impedances must be controlled to prevent mismatches and reflections. Otherwise, you end up with intersymbol interference and other effects that cause errors in digital links. "Typically, you'd use a 2D solver because you just want to design the cross section of your transmission line," says Hinz.
That's fine for a straight trace because a 2D solver accomplishes a cross-sectional analysis of the trace at one point and treats it as a lumped element and outputs it as an RLC model. "You could characterize a 3D structure like a via with a lumped-element 2D solver," says Jonathan Smith, product marketing manager at Ansoft. At relatively low speeds, that RLC output would be acceptable to an experienced designer who is comfortable with analog effects.
But at high speeds, or in cases of nonuniform traces, 3D structures need to be characterized more accurately with distributed models. That's when a 3D solver is used to output a model as a distributed RLC network. "At that point, you lose the ability to just eyeball it and say the capacitance is too high or the mutual inductance is too high," says Smith. Looking at the waveform requires signal-integrity tools.
3D solvers also are required when ground planes aren't ideal. For instance, if the ground plane has cutouts or other irregularities, a 2D solver will be unable to characterize traces that encounter those nonuniform areas of the board.
Heavy-duty signal-integrity analysis tools, especially those involving 3D field solvers, aren't for everybody or every board design, though. All board designers should have an environment that produces pc boards with adequate functionality, on schedule, within budget, and in a fashion that's manufacturable. To that last point, relatively affordable design environments are available that go beyond board layout to show how the finished board will interface mechanically with the system.
One example, Electronic Workbench's Ultiboard layout software, includes a mechanical CAD module. This utility lets users draw accurate front panels, enclosures, and other mechanical pieces, ensuring that their board will mesh smoothly with the packaging it will ultimately reside in.