Power Formats: You Can Have It Your Way

One area in which both formats need to improve is the handling of embedded IP. A design team or third-party company will often provide RTL for a block that can be integrated into a system-on-achip (SoC) design. In this case, there may be a number of options for low-power design in the IP, but the IP provider will want to limit the options to ensure that the IP will function correctly.

For example, an IP block may be constructed with several power-supply inputs, all connected to a single always-on supply. But if several voltages or several powerdown sequences are desired, the IP provider needs to constrain the possibilities. Neither CPF nor UPF provides a clean way to do this today. For UPF, the P1801 committee is actively discussing improvements, and Cadence may be internally considering improvements as well.

CPF and UPF cover 90% of the same concepts using completely different syntax. For voltage domains, power domains, retention cells, and other common lowpower design styles, low-power designers can represent their intent in either format. Yet there are several areas of difference between the formats. Notably, UPF requires Liberty to define library cells such as level shifters. In the next year, there won’t be any “convergence” onto a single power format. But designers can constructively use both formats to get their chips taped out.