About three years ago, timing closure for
large system-on-a-chip (SoC) designs
began to develop into one huge headache.
Every EDA vendor’s toolset had
its own interpretation of timing constraints,
and there was little or no consistency
between those representations.
So if you used tools from more than
one RTL-to-GDSII vendor, you were in hot water. Designers
began clamoring for a single open standard for the modeling
of nanometer timing effects, and EDA vendors agreed that a
single modeling standard for timing would streamline verification
and implementation flows.
The only problem was that the industry did not end up
with a single standard for the modeling of nanometer effects.
Instead, as is the EDA industry’s fractious wont, it served up
two: the Effective Current Source Model (ECSM) and Composite
Current Source (CCS) models. And while two standards
are better than 20, they still aren’t as good as one.
Today, a parallel scenario is unfolding, only this time it’s in
the power domain. Once again, EDA vendors are charting a
typically divisive course that will result in multiple standards
for the specification of power intent.
Two groups have coalesced, each claiming that it is “userdriven”
and giving priority to “interoperability.” How they
define interoperability, though, may not be to the liking of
the design community. So who is behind these two emerging
power-intent standards? Why are there two standards and not
one? How are they the same, and how are they different? And
why might you choose one over the other?
A Tale Of Two Standards
On May 22, 2006, Cadence Design Systems announced the
launch of the Power Forward Initiative (PFI), which it claimed
would “address obstacles to lower-power IC design facing the
electronics industry.” PFI members would gain access to the
first version of the Common Power Format (CPF), a means
of specifying power intent and constraints in a single file that
would be applicable across the design flow. CPF would constitute
the basis for a holistic approach to the specification of
power intent that would ride atop the existing infrastructure.
“CPF was developed in 2006 and made available to everybody
at the end of that year,” says Pankaj Mayor, Cadence’s
group director of business enablement. “It’s been used in a
production environment in our products since January of 2007
and in several other EDA companies and IP companies in
their deliverables. Customers have had over 50 tapeouts with
our low-power solution,” claims Mayor.
According to Frank Childers, the Silicon Integration Initiative’s
(Si2’s) director of business operations, the ecosystem
now supporting CPF includes 38 companies, including large
systems houses, IP vendors, foundries, and service providers.
In December of 2006, Cadence donated the CPF to Si2
with an eye toward launch of a standardization effort. Meanwhile,
a parallel effort was born of a meeting held at the Design
Automation Conference in July of 2006. There, a number of Cadence competitors, notably Synopsys,
Magma Design Automation, and Mentor
Graphics, met with several systems
houses, among them Texas Instruments
and Nokia.
Citing a lack of openness and haste in
the PFI/Si2 process, the group enlisted
Accellera for its own standardization
vehicle. Dubbing the competing format
the Unified Power Format (UPF), a kickoff
meeting in September of 2006 yielded
an accelerated timetable for standardization
and subsequent donation to the
IEEE (Fig. 1).
“UPF was actually instigated by users
who saw what Cadence was doing with
the Power Forward Initiative and CPF
and realized that Cadence was out to control
and define it such that it wouldn’t be open,” says Steve Bailey,
product marketing manager for Questa in the Design for Verification
and Test Group at Mentor Graphics and chairman of the
IEEE P1801 Low Power Working Group. “Users were afraid that
the other vendors whose tools they use wouldn’t be able to be full
partners in it. They wanted something truly open.”
The two groups have wrangled ever since, amidst calls from all
corners of the industry for the standards efforts to converge. Backers
of the CPF have insisted that Si2 and its Low Power Coalition
(LPC) is the proper venue for convergence, while the UPF camp
has pushed for the IEEE as the umbrella organization. Further
squabbling erupted over patents and IP issues.
Where Things Stand
Unable or unwilling as they are to come to terms with each other
thus far, the two camps have pursued their agendas separately.
The Si2’s Low Power Coalition released the CPF 1.0 specification
in March of 2007; the format is freely downloadable from
the OpenEDA.si2.org Web site. Meanwhile, Accellera’s board of
directors approved the UPF 1.0 standard in February of 2007 and
has since passed the standard into the hands of the IEEE’s P1801
Low Power Working Group.
One insider with a direct view into both the CPF and UPF development
efforts is Gary Delp, LSI distinguished engineer, office of
the CTO. Delp is vice chairman of the IEEE P1801 Working
Group and a former member of the Accellera UPF Working Group.
He also serves as an architect in the Low Power Coalition of Si2.
“It is very much in the user’s interest to have a single format,”
says Delp. “I would very much not like to get into VHDL and
Verilog kinds of dual maintenance issues.”
In fact, just about every interested party on all sides of this controversy,
be it EDA vendors, representatives of standards bodies, or
tool users, echoes the desire for a single standard. “We absolutely
agree that there’s benefit for EDA companies as well as for designers
to have one standard,” says Cadence’s Pankaj Mayor.
As to why Cadence and the PFI has declined to pursue convergence
between the standards, Mayor cites parochialism and a
lack of broad support. “Why does Cadence decline to participate
in the IEEE P1801 Working Group? That’s really a UPF effort,
just moving from Accellera to IEEE,” says Mayor. “And, representation
in the group is fairly limited.” Voting membership in
the P1801 Working Group includes Accellera, ARM, Intel, LSI,
Magma, Mentor Graphics, Synopsys, and TI.
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