Rail-Signoff Analysis Ensures SoC Power Integrity

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If you haven't yet added the clock tree to the netlist, be sure to account for its power consumption. The clock tree can consume a surprisingly large portion of a design's dynamic power, especially in designs using 90-nm and smaller technologies. This power consumption depends on the design architecture, the operating conditions, and the process technology.

Working with rough estimates for toggle rates and using either of the flow's toggle methods, Astro-Rail can scale the estimated power to match a specified power value. As an alternative, spreadsheet estimates usually offer acceptable accuracy because you can use information such as energy-per-transition and a mapped gate-level netlist to calculate the power.

You can use the spreadsheet power estimates in the same way as the rough toggle-rate estimates, or, you can have the rail analysis tool propagate the toggle rates through the logic cones. In fact, running the flow using clock-domain-based switching activity invokes the latter method of power estimation. The statistical propagation feature (using PowerCompiler technology) analyzes the combinatorial logic functionality to determine the toggle rates for each net. It can achieve more realistic power estimates even if your toggle-rate estimates are somewhat pessimistic.

Undoubtedly, the best suggestion for both power-integrity planning and analysis is to start as early as possible. By starting early and integrating these methodologies into the overall design flow, you avoid many problems that become difficult to correct later in the flow. The practices described here can give you a head start on implementing a rail analysis flow that's essential to ensure the performance of today's SoCs.

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