Reducing The Design Impact Of DFT In The Nanometer Era

Normally, scan patterns load scan cells with the bits that are necessary to detect targeted faults. Only a small fraction of scan cells can be loaded with useful values, though. All other scan cells are loaded with random values. One basic approach with compression techniques exploits the fact that most scan cells can be filled with pseudorandom data. The pseudorandom filling provides some coverage of non-targeted faults.

A decompressor can operate as a transform function to convert tester-loaded bits to specific bits within the scan chains. The non-specified bits are randomly filled from the on-chip decompressor and not from the tester. Consequently, each pattern can be loaded with up to 100 times fewer test cycles/bits.

In an example of a circuit with test compression, a decompressor and compactor are added to the design (Fig. 4). They connect only to the design’s scan chains and have no impact on the functional logic. This example shows a device with two scan channels that are loaded by the tester. Internally, the design is configured with many more internal scan chains than normal.

A traditional scan design with two channels would result in one bit being loaded into each of the two chains with each clock pulse. The compression technique results in two bits being loaded from the tester, as is the case with standard scan. But the decompressor can supply 100 or more bits to many internal scan chains with the same clock pulse.

Since there are many internal scan chains, the lengths of the chains are much shorter than normal. Hence, the scan chains can be loaded with dramatically fewer tester cycles. The quality and coverage of the test-compression patterns are the same as with traditional scan.

Test compression can result in over 100 X fewer tester cycles. For designs that don’t require 100 X compression, some of the compression capability can be used to reduce the scan I/O pins necessary for test. This is possible even to the point of only using one scan channel.

For instance, adding compression to a design with six scan chains can both speed up test time and reduce scan-I/O requirements. If the design has 60,000 scan cells, using six scan channels would normally result in taking 10,000 cycles to load each pattern. For this example, the design with compression could be configured with 600 internal scan chains and six external scan channels, providing an opportunity for 100 X compression.

But if only 20 X compression is necessary to apply all of the patterns within the desired time, some of the compression can be used to reduce the I/O pins. In this case, the scan-I/O pins can be reduced by 3 X to two channels and configured with 200 internal scan chains. As a result, the scan-I/O pins are reduced by 3 X while the patterns are applied more than 20 X faster. These two channels can load each pattern in 300 cycles (60,000 cells/200 internal chains).

The ability to reduce scan channels can dramatically reduce the design impact due to test. Fewer scan channels means less pins for test in the design, simpler test fixturing, and simpler test requirements. Reduced pin-count testing is also possible if boundary-scan features, intended to test device I/O, are configured as scan cells (Fig. 5).⁴

This approach reduces tester pin access enough so multiple die or devices can be tested in parallel. Such a test approach, known as multisite testing, can dramatically improve tester throughput.

Test compression also supports modular and hierarchical implementations. Therefore, the decompressor and compactor can be inserted within individual blocks. The top level of the design doesn’t require any compression logic. Additionally, the scan-channel routes for each block can be cut to one channel using embedded test compression.

References:

1. B. R. Benware, et. al., "Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs," VLSI Test Symposium 2003.
2. M. Beck, et. al., "Logic Design for On-Chip Test Clock Generation –Implementation Details and Impact on Delay Test Quality," DATE 2005.
3. J.Rajski, et al., "Embedded deterministic test for low cost manufacturing test," Proc. ITC, pp. 301-310, 2002.
4. J. Jahangiri, et. al., "Achieving High Test Quality with Reduced Pin Count Testing," ATS 2005.