VERIFYING AND ANALYZING LOW-POWER DESIGNS
Verification tools must be able to check details such as power-down-switch-enable networks, even though name mapping can be a challenge. State-retention power gating (SRPG) cells pose particular verification challenges. The master latch in the flipflop connects to switch power (VDD), while the slave connects to always-on power (VRET) (Fig. 5a). When the clock is disabled (gated) and retention (RET) is enabled, the master latch powers down while the slave latch retains the state (Fig. 5b). At wakeup, power switches back on for the master, RET is disabled, and only then is the clock enabled.
The best way to make sure that such power-up and power-down sequences work correctly throughout the design is to analyze the logic using formal proofs. In fact, formal verification is essential to ensure that low-power optimizations done in logic synthesis, physical synthesis, and place and route don't introduce logical errors.
Low-power design requires several types of analysis, including power integrity analysis that checks for IR-drop and electromigration effects for multiple voltages. The tools must consider chip temperature (thermal distribution), because hot spots can contribute to leakage power surges and add to the chances of electromigration within the wires.
Traditionally, accurately modeling cell delays for a particular voltage level required characterized timing views for that voltage level—a requirement that involves a great deal of characterization. Even then, voltage variations due to IR drop affect timing in ways that require additional analysis.
Fortunately, current-source models make it possible to predict the effects of voltage variations on delay to within 2% of Spice simulations, including accounting for IR drop. Moving to libraries and tools that use such models will greatly reduce the work involved in verifying designs with multiple power domains and enable faster timing closure. Otherwise, it's a good idea to limit the number of different supply voltages.
Ignoring the impact of IR drop on timing can cause additional setup or hold violations due to the varying operating voltages around a design. Additional delays caused by IR drop on the signal paths create setup-time violations, while additional delays on the clock network create hold-time violations. Performing timing analysis at fixed voltages will never show these additional violations because operating voltages are treated as constant.
WHAT'S NEXT
The use of multiple power domains raises issues for design reuse. Specifically, how do you design blocks for power shutoff while making the RTL reusable? How do you ensure that the functionality isn't altered when the blocks are shut down? How do you simulate the effect of level shifters and isolation cells? Do you create a mixed gate and RTL simulation for these conditions?
Today, specifying power intent for every design stage is cumbersome and ad hoc. Engineers implementing advanced low-power techniques face these challenges right now. As more and more engineers look toward these advanced techniques as the only option available for power reduction, the need to support them holistically becomes more apparent.
Hence, engineers should demand that their tools talk and understand in a similar manner when it comes to power. The simulation tools must talk to the synthesis tools, and the synthesis tools must talk to the implementation tools—using the same understanding as to how the designer has specified the design intent for power.
A common specification of power intent understood by all of the tools, from architectural specification to functional verification to implementation, could simplify the design process enormously. What's needed is an infrastructure to capture power intent throughout the flow. This level of support is imperative for any future tools, since these engineers don't want to compromise anything to realize their power-reduction needs.
Mohit Bhatnagar is currently responsible for marketing digital prototyping and physical synthesis products for Cadence Design Systems Inc. (www.cadence.com), San Jose, Calif. He holds a a PhD in electrical engineering from North Carolina State University, Raleigh.
Jack Erickson is product marketing director for RTL synthesis at Cadence Design Systems Inc. He holds a BSEE from Tufts University, Medford, Mass.
Anand Iyer is product marketing director for the Encounter digital IC design platform at Cadence Design Systems Inc. He holds an MBA from Santa Clara University, Calif., an MSEE from the University of California, Santa Barbara, and a master's of technology in reliability engineering from IIT, Bombay, India.
Pete McCrorie is responsible for DFM product marketing at Cadence Design Systems Inc. He holds a master's in physics and electronics from the University of Liverpool, United Kingdom.
References:
- Poletti, Therese, "Taming data centers' appetite for energy," San Jose Mercury News, Feb. 1, 2006, www.mercurynews.com/mld/mercurynews/business/13762620.htm.
- Lammers, David, "Leakage control needs multi-pronged ATTACK" EE Times, Feb. 5, 2005, www.eetimes.com/news/latest/showArticle.jhtml?articleID=174900266.
- Iyer, Anand "Demystify power gating and stop leakage cold," Power Management Design Line, March 3, 2006, www.powermanagementdesignline.com/howto/showArticle.jhtml;jsessionid=YCNF5WEIY1QKKQSNDBESKHA?articleID=181500691.