Designers also are experimenting with general-purpose programming languages, like C, C++, and even Java, for hardware modeling and simulation. In significant design projects, it's becoming accepted practice to perform the initial design exploration in a general-purpose programming language, typically C or C++, before implementing the design in an HDL.
Designers are experimenting with C or C++ programming languages as alternatives to the traditional design languages. The existing RTL-based design methodology is successful because an RTL model in Verilog or VHDL can be verified by simulation or formal means and then transformed into a design implementation in a way that was proven correct. C/C++ lacks the necessary features to unambiguously model hardware designs, so some engineers are proposing language modifications or extensions to make it more appropriate for their purposes.
The key to using C/C++ as a hardware description language is to provide the required data types, concurrency model, and hierarchy support. Without these features in the language itself, any method of hardware description using that language becomes arbitrary and loses the consistency between execution results, or simulation, and synthesis results. In the case of C or C++, the required HDL semantics can be provided by C++ classes as an extension of the language to bridge the gap.
Several vendors have proposed extensions such as these to a general-purpose programming language like C/C++, or to a hardware design language like Verilog. This is an attempt to overcome the limitations of any single language in hardware modeling and simulation. These languages are either hybrids of two or more existing languages, or supersets of one language or more.
According to Peter Flake, cofounder and chief technology officer of Co-Design Automation, such a language requires hardware features, including concurrency, events, and timing, along with software features like user-defined data-type structures, pointers, and storage. To better support verification, the language also should include hierarchical and concurrent state machines, support for dynamic arrays and queues, the ability to replicate some of the process-management features found in operating systems, plus the ability to monitor and execute a protocol.
A Superset-Type Language
An example of a superset-type language is Co-Design Automation's SuperLog (Fig. 3). Based on Verilog, it's extended with features from both C and VHDL. It includes the C typedef instruction for creating user-defined data types, C operators, and control constructs. SuperLog produces a number of modifications that make it more of a cross between a general-purpose language and an HDL. This means that it has the potential for possibly using a single environment for end-to-end specification and design.
Utilizing a general-purpose programming language for initial system specification additionally creates the problem of translation into a usable hardware description. When the design process is finished and the high-level design parameters have been decided upon, the resulting program must be translated into an RTL model in Verilog or VHDL, so that the design can be implemented using standard simulation and synthesis design tools.
This rewriting step might be termed a design gap because it's not only an entirely manual process, it's a complete rewrite of the design from one type of language to another as well. Resulting from this is a host of problems emanating from the inability to verify the equivalence of the two design representations. There's simply no guarantee that the design prototyped in a general-purpose language is the same design that's implemented using, for example, VHDL.
Tools like CynApps' Cynlib come in here. Cynlib's approach is similar to that of SuperLog, where an architectural model can be iteratively refined from a very high level to a detailed implementation model in a continuous fashion. The whole time, the model is executable, so there's no discontinuous jump from one representation to another. At the lowest levels, the execution of the model provides a cycle-accurate simulation of the final hardware. Once the simulation tools can be fully extended across the various languages that are used at different points in the design process, engineers will be able to work at higher levels of abstraction while shortening debugging and verification time later in the cycle.
In practice, many tools support mixed-language simulation. For in-stance, for design definition, Cadence's SpeedSim accepts any combination of synthesizable Verilog constructs—RTL or gate-level, including UDPs. Cadence supports C/C++ for test bench construction, claiming that these languages make the most efficient test benches. But, SpeedSim also accepts many Verilog behavioral test bench constructs. From Model Technology, ModelSim offers a combination of mixed Verilog and VHDL code simulation, as well as either language individually.
The Role Of IP
IP plays a key role in the design-cycle time for complex SoCs and other complex designs. Today's SoC designs reuse IP from earlier, or legacy, designs and third-party developers. The IPs can be represented in various formats, such as VHDL, Verilog, or C. This requires that simulation and verification tools understand multiple design languages, and that the circuitry, including these IPs, function correctly.
Simulators typically work with IP as a black box, because module verification isn't necessary. Model Technology's ModelSim offers the possibility of third-party IP providers delivering compiled code. Then, this is combined in the simulator with code that's implemented by designers to accomplish a full design for simulation.
With SoC designs extending into several million gates, simulation performance and memory issues become critical. As a result, simulation environments are beginning to go more toward 64-bit platforms, such as Sun SPARC and Intel Itanium processor systems. Primarily, the need is for memory and storage capacity capable of manipulating very large code models. Model Technology has already announced its support for selected 64-bit simulation platforms, and others will follow over the next year.
When using high-density FPGAs to create increasingly larger and more complex designs, simulation represents a way to more fully debug and verify the design in a shorter period of time. State-of-the-art simulation tools coupled with other advanced verification tools and techniques can provide design engineers with a powerful arsenal to attack the burgeoning verification challenges. Advances such as higher performance, 64-bit platform support, and more alternatives in mixed-language and multilanguage support, enable engineers to spend less time in the simulation phase of the design.