Tools for power design must be able to estimate floor plans. They also must generate a thermal heat map of the estimated floor plan and generate a trend analysis, which is a graphical representation of how changes affect power consumption. These functions should interact with a scheduling graph that helps to identify potential timing problems because low power that doesn't meet timing will never tape out(Fig. 3).
The International Technology Roadmap for Semiconductors (ITRS) for 2001 forecasts that high-performance ICs will dissipate 200 W within the next five years. The easy power reductions afforded by cutting the supply voltage from 5 to 3.3 to eventually 1 V or less cannot keep up with the other factors driving power consumption. For most systems in existence, power is a function of clock frequency, total capacitance, and voltage squared (P µ fCV2). The total switching capacitance is a function of the gate count, and this is where the problems arise.
For high-end system chips, gate counts are now measured in units of 10 million. The gate capacitance is swamped by the interconnect capacitance, which is growing to over 10 km of total length. So power is increasing as a linear function of the product of capacitance and frequency, and both numbers are growing in line with Moore's Law, doubling about every 18 months.
Jerry Frenkil, vice president of advanced development at Sequence Design Inc., notes that the problems to be solved are changing with the designs. Thermal issues are just starting to become significant to most designers. These issues aren't just at the chip level, but at all of the higher levels of the system too. Therefore, designers must change their approaches to design problems and solutions.
Temperature effects include changes in delay, power handling capabilities, power analysis, and component lifetimes. In addition, electromigration becomes worse at higher temperatures. Not a static parameter, temperature varies in time and in place on the die. The amount of signal activity within a chip must be traded for performance, but both are becoming power limited.
An example of this trend is Transmeta's Crusoe chip. Originally de-signed for laptop computers, it's now moving into blade servers due to limits in the power dissipation capabilities within the boxes. Large systems cannot afford to add additional blade servers, even though there may be space available within the rack, be-cause of the power densities within the enclosures. Blade servers are failing due to the heat from one board overheating adjacent boards.
Lee Hansen, product marketing manager at Xilinx, states that design flows need to change, from the reactionary phase of correcting problems after they appear, to a proactive flow that looks at power and thermal issues early in the design stages and aids in the prevention of downstream problems.
The design tools for some FPGAs even look at various forms of power consumption. Xilinx has a tool originally developed for ASIC designers who wanted power analysis for the designs they were developing in the FPGAs.
There are two sets of users for this tool. The first, complex programmable logic device (CPLD) designers, looks for low-power implementations (like battery-powered equipment) and needs all possible information about power consumption within the design. The other group is designers who use many chips within their designs (such as network equipment) and need to address the overall thermal issues of the design.
These high-performance designs need to consider parameters such as available heatsinking, thermal flows, and the effect of clocking across multiple chips to manage the total power consumption and keep all the chips within reasonable thermal parameters.