Tharas Systems' Hammer 100 accelerator also offers the inherent compilation advantages of a custom architecture. It can compile a 15-Mgate design in under an hour on a single workstation.
Custom architectures can take great advantage of transaction-based acceleration. In Cadence's Palladium II platform, designs are partitioned into two different models. The behavioral portion runs on the workstation in C or SystemC while bus-functional models, which require more hardware resources, are mapped into the accelerator. Thus, most of the activity is on the hardware side of the equation. The same testbench and transactors can be reused in simulation and acceleration.
Tharas Systems' Rich Curtin, vice president of marketing, sees a significant upswing among Hammer users in adopting transaction-based verification. "We've seen transactions used more in networking applications, which involve lots of data passed back and forth between the stimulus generator and the design under test (DUT) mapped into the accelerator. But as customers begin writing complex and reusable testbenches, we'll see TBV getting into the mainstream," says Curtin.
Use of transactions is by no means limited to custom architectures. EVE's ZeBu-XL, an FPGA-based platform, features a testbench-to-DUT interface that's optimized to support transactions. "We even do that when you apply the testbench on a cycle basis," says Lauro Rizzatti, vice president of marketing and general manager of EVE-USA. In fact, when used with hardware, transactions can even replace cumbersome and difficult-to-reuse in-circuit emulation test beds (see "Transactions Will Melt Away Yesterday's ICE," p. 52).
Assertions are also becoming an important component of hardware-assisted verification. They allow designers to put built-in triggers into their code. Failures in assertions can tell verification engineers which block is the problem and enable them to quickly isolate the bugs. In Cadence's Palladium II, assertions are ported directly to the hardware, where they can be run at full speed. Users can either stop their verification session when an assertion failure occurs or continue while recording the failure.
"We're bringing more methodologies used in simulation tools into the hardware-based environment," says Cadence's Avinun. "Assertions is one of those new methodologies being used today mainly in simulation, but we think it will start to be deployed more in acceleration and emulation in the future."