HARDWARE DESIGN is a process of refining an idea from a highly abstract form to a concrete, physical implementation. Along the way, a design is continually transformed from a given state of abstraction to another less abstract representation, finally ending with physical design. Those transformations are achieved through synthesis.
For the past 15 years, synthesis primarily has meant transforming an RTL design description to a gate-level netlist. Synopsys' Design Compiler, fueled by the emerging Verilog language standard, represented a new design paradigm that helped designers manage the spiraling complexity of LSI chips.
But as electronic-system-level (ESL) design emerged, EDA tool vendors began providing tools for synthesis of designs from higher levels of abstraction into RTL. It's hard not to see close parallels between the state of high-level synthesis today and the early days of Design Compiler, when it battled for acceptance in a design community that was loathe to give up its beloved schematics.
HOW HIGH IS UP?
Why would designers want to move up in abstraction in the first place? There are three primary reasons, according to Jeff Jussel, vice president of marketing and Americas General Manager at Celoxica.
"One reason is when you have both hardware and software in the system and it's a benefit to have a common language (most often C) between the two," he says. "A second is when you're working with an algorithm that's just too complex to write in RTL. The third is verification. C is used for modeling because it's far faster than RTL in simulation (due to the absence of timing information)."
A few classes of synthesis reside above RTL, more or less categorized as algorithmic, coprocessor, and behavioral. One case that stands out is a kind of reverse synthesis in which C-level models are synthesized from existing RTL (see RELATED ARTICLES: "Synthesis In Reverse?" at the top of this page.).