RTL: NOT DEAD YET
While many designers explore their options above RTL, RTL synthesis hasn't gone away. But even RTL synthesis is creeping upward in abstraction.
For example, Bluespec's tool accepts an untimed design description in a proprietary flavor of SystemVerilog. Bluespec's approach uses what it calls "rules and methods" to describe parallelism and block-to-block interfaces. "Rules and methods" are embodied in extensions to SystemVerilog. The resulting amalgamation is what the company calls Bluespec SystemVerilog.
"Traditional behavioral synthesis is very good at taking a tightly nested for-loop and parallelizing that into hardware," says George Harper, Bluespec's director of marketing. "But the bulk of IP out there doesn't fall into that category." Bluespec has tried to subtly raise the level of abstraction of RTL synthesis by adding these rules and methods, which can be likened to assertions.
An important consideration in today's synthesis environment is the proliferation of implementation choices. Designers can choose from FPGAs, ASICs, and structured ASICs. As a result, it's crucial that synthesis tools be tuned to the architecture of the chosen implementation.
Synplicity attempted to address this requirement in its range of synthesis tools. The company recently introduced graph-based physical synthesis for FPGAs. With this capability, Synplicity's tool can perform simultaneous placement, optimization, and routing. It then passes forward the placement information and the netlist to the FPGA vendors' routers.
Similarly, Synplicity has worked closely with structured-ASIC vendors such as LSI Logic, NEC, and Fujitsu so its physical synthesis tools can offer close correlation between the tools' timing analysis and the ASIC vendors' back-end flows.
Synplicity uses a technology it calls Sensitive Net Analysis and Prevention to reduce the probability that variations in routing will cause a correlation problem (Fig. 3). This way, the synthesis tool ensures that the placed-gates design still meets timing after detailed routing.
"In our experience, it takes a pretty small amount of area expenditure to tighten up the prediction," says CEO Ken McElvain.
The granddaddy of all RTL synthesis tools, Synopsys' Design Compiler, still commands an overwhelming market share in its domain. The latest revision, Design Compiler 2005, brings more accuracy to the table in an effort to have its timing and area reports correlate more closely with physical implementation.
To this end, Synopsys did away with wireload models in Design Compiler and is pushing more physical information forward into the synthesis step. Meanwhile, the company managed to keep the look and feel of the tool consistent.
Magma Design Automation subscribes to a similar philosophy—accuracy in logic synthesis with respect to the physical domain. "The value in RTL synthesis is in giving the designer insight into what the physical implementation is likely to be," says Yatin Trivedi, Magma's director of product marketing.
"The game has shifted from 'give me the most optimized netlist' to 'help me create better RTL and complete the constraints,'" Trivedi says. In Trivedi's and Magma's view, physical synthesis is the best opportunity for real improvements in timing, not logic synthesis.
"Physical synthesis provides an opportunity to reimplement the datapath," says Trivedi. "Traditionally, people have fixed their datapath elements. Then they run into problems and try to fix them in the back end. What you really need to do is implement datapath synthesis dynamically or on the fly."
In its RTL Compiler technology, Cadence takes an approach it calls global logic synthesis. RTL Compiler doesn't create an implementation randomly and then optimize. Rather, the tool considers all axes of optimization during the global surveying process. According to Chi-Ping Hsu, corporate vice president at Cadence, global synthesis has great impact in terms of power optimization.
"The optimization for leakage power tends to be more in sync with area objectives, while optimization for dynamic power tends to be contrary to area objectives," says Hsu. "When you add multiple voltages, it really makes the traditional incremental approach very difficult. Runtimes are extremely slow, and results are suboptimal."
In the physical-synthesis realm, as with logic synthesis, EDA vendors have strived for greater accuracy. Synopsys updated IC Compiler to extend physical synthesis to cover both placement and routing.
Just as earlier generations of physical synthesis closed the gap between synthesis and placement, Synopsys' Extended Physical Synthesis (EPS) technology brings placement, clock-tree synthesis, and routing into close alignment. The net effect is the greater visibility of placement into clock-tree synthesis, and the results of that previously disparate process can be anticipated so it's accounted for during placement optimization.
EPS technology also enables clock-tree synthesis to anticipate and guide routing. Furthermore, routing can modify placement and locally perform resynthesis to complete the design where needed.
What could the future hold for physical synthesis? One indication comes from Zenasis Technologies. Its flagship tool, ZenTime, performs transistor-level optimization of standard cells to precisely tune them to meet timing objectives.
"In the late 1980s and early 1990s, logic synthesis was the factor that changed standard-cell design, followed by physical synthesis, which has now taken over the whole synthesis domain," says Sunil Mudinuri, marketing manager at Zenasis. "We believe that in the future, the new synthesis domain will be what we're calling flex-cell or design-specific cell synthesis."
Today, most standard-cell designs are being done on fixed libraries. Zenasis proposes imposing a layer, or wrapper, around the standard cells that would enable ESL tools to replace them, as necessary, with cells that would satisfy specific timing, area, and power constraints.
Zenasis' technology operates at the transistor level, giving the tools a good deal of insight into what's happening inside the cells. In the flex-cell concept, more physical information can be piped into the ESL tools for a better estimation of a given implementation.
It's almost ironic that a futuristic concept for physical synthesis would reach all the way up to the ESL level. But given the path taken by synthesis to this point, it's not surprising that EDA vendors would seek to drive physical information as high in the flow as possible.
In a sense, Zenasis' concept closes the circle, bringing the end point of the design process—physical design—around to the front end. This is, in all likelihood, the path that the EDA industry will, and must, traverse if Moore's Law is to survive long into the 21st century.