The industry shift toward design reuse is now progressing from block-level to system-level design. To improve system-on-a-chip (SoC) productivity, many organizations are turning to SoC reuse platform solutions. These application-specific reference designs take advantage of previously created SoC architectures. This approach allows designers to reuse major portions of entire chips instead of just a few components.
The goal of the SoC reuse platform is to improve the time-to-market of multimillion-gate SoC designs by facilitating the reuse of design architectures, components, and verification suites at the chip level. This greatly increases the impact of design reuse and promotes better system solutions. SoC platforms enable design reuse productivity by changing the focus of SoC design from block-level design creation to system-level design composition.
An SoC reuse platform is a reference design that defines all or part of the architecture for a particular application. One defining aspect of a platform design is that it's at least architecture specific, if not application specific. As an SoC design, the platform will include at least one microprocessor core, one DSP core or more, and on-chip memory, as well as a number of pre-existing IP peripherals. Platform designs typically contain only a small amount of new logic that's specifically designed for the system.
Bus connections are the most important structures in a platform design, not the processor. All blocks in the design are built to communicate with each other as well as with a library of extensible components. The platform design is intentionally modular. That allows for the swapping of configurable blocks in order to quickly produce similar—but unique—SoC derivatives.
The experience of those from Mentor Consulting has shown that to attain the most value from an SoC reuse platform, the reference design should support an application or architecture that's expected to become the basis for many SoC designs. A platform design requires from three to ten derivative SoC designs to return the initial investment. The actual break-even point depends on the application and the level of automation built into the SoC reuse platform.
Not every design warrants this type of investment. But applications requiring many versions of similar SoC solutions can greatly benefit from this approach. There are many good examples of appropriate applications for platform designs in wireless telecommunications, networking, and consumer electronics.
A typical SoC derivative built from a reuse platform might have over 70% of its design content coming from reuse (Fig. 1). This includes the design architecture, the bus connection schemes for the components, and the functional verification suite for the design. To meet performance and size goals, the memory blocks as well as the processor and DSP cores are normally included in hardened form. As such, it's the availability of these cores that determines the silicon technology used by the SoC design.
Soft cores provide the standard functions for the application and the device peripherals. In the creation of a platform design, these soft cores must be modified to communicate via a common bus interface. This investment ensures that the reusable components can be easily integrated.
The remaining 30% (or less) of the SoC derivative is comprised of logic that's either created from scratch, adapted from legacy components, or else acquired from third-party providers. This new logic has to also be modified to connect to the design and bus standards dictated by the platform design.
The strength of the SoC reuse platform is in the known value of the architecture. In any design-reuse scenario, the reusable components must adhere to the requirements of the SoC. For typical SoC design, though, these requirements change greatly from design to design depending upon the needs, experiences, and whims of the engineering team. As a result, making a block "reusable" is normally associated with making it work in any possible combination of design styles and tool flows. This is an unrealistic goal for most components, and a terrible time sink for any design organization that goes down that path.
By contrast, the requirements for SoC designs remain constant in a platform design. The reusable components are modified to meet the standards set for the reference design, and only those standards. Reusing design standards, bus connectivity requirements, verification suites, and tool flows allows the platform environment to be tuned to maximize design productivity.