With 0.13-µm processes coming online and 0.10-µm processes waiting in the wings, the stage is set for ASIC and system-on-a-chip (SoC) designs to grow exponentially larger and more complex. Such designs are outstripping the capacity of today's verification systems, creating a bottleneck in the design process that can delay or even prevent getting end products to market.
Verification of IC designs at the system level is more complicated and difficult than ever. These designs can't be exercised fully unless the design team's verification system can run actual application code on them. If the design team doesn't have a verification system with enormous capacity at its disposal, this process can take a very long time, if it's possible at all. In addition, the designers typically must run multiple iterations of the verification process. Again, the lack of capacity can be a killer. The resulting "verification gap" is quickly attaining status as Public Enemy No. 1 in the IC design community.
Quickturn's CoBALT Ultra design verification system directly addresses this need, offering massive capacity of more than 100 million ASIC gates and 64 Gbytes of memory (Fig. 1). The single-chassis system accommodates even the largest chip and system designs, while providing the engineer with a full set of tools that includes simulation acceleration, synthesizable test bench acceleration, and in-circuit emulation.
CoBALT Ultra is the latest member of Quickturn's Concurrent Broadcast Array Logic Technology (CoBALT) family. It sports dramatic gains in functionality compared to its predecessor, the CoBALT Plus. Using a massive array of newly designed custom emulation ASICs, the Ultra delivers more than five times the capacity and double the runtime performance of the older system. The concurrent processors are built on IBM's 0.12-µm, seven-layer copper process technology. (It's not entirely accidental that the initials for CoBALT Ultra comprise the chemical symbol for copper.)
The system can be scaled to support up to 112 million ASIC gates with an architecture that maintains constant in-circuit performance, even as designs grow to encompass multiple system boards. Thus, designer productivity is maintained as designs expand.
System-Level Verification
The CoBALT Ultra system isn't a followup to Quickturn's earlier CoBALT Plus system, but rather to its recently announced Palladium system, which has a capacity that can be expanded up to 16 million gates. This is more than adequate for the high-end, mainstream IC designs done today, as well as for those done in the near future. Meanwhile, the CoBALT Ultra system stands ready to serve the system-level verification needs of extremely high-end designs, offering the gate-count and memory headroom needed to do the job for quite some time to come. Both systems share the same fundamental silicon technology, and both represent a dramatic departure from FPGA-based simulation acceleration and emulation (Fig. 2).
A scalable architecture allows designers to use the system's entire capacity without negatively affecting runtime performance. RTL-to-verification time averages more than 4 million gates per hour using only a single workstation. Debugging designs of 10 million gates or more requires such RTL compile speed. As a result, full compiles of small designs, as well as incremental compiles of large designs (probe compiles) can be completed in minutes. This combination of fast compile times and minimal computer resource requirements lets designers turn entire designs several times in one day without tying up multiple computers.
"The fact is that SoCs are finally becoming real for a lot of designers," says Mike Butts, Cadence Fellow, a co-inventor of logic emulation and a key member of Cadence's Systems Solutions Business Unit. "To exercise an SoC properly, you need to boot the real-time operating system and run some real data on the application. The data sizes are very large, too, and take lots of cycles."
This level of verification is very difficult to do purely in software. It takes hardware acceleration. Another key aspect of the overall task is how the verification load is broken up. "When software is involved, you typically have a single thread of execution on which you need to run millions of cycles," Butts says. In many cases, particularly when verification loads involve regression testing or other similar tasks, the job can be handled nicely with a compute farm of PCs or workstations. A given test might comprise between 1000 and 10,000 cycles in such situations.
But when it comes to actually running software on a design, that single thread of execution must run for millions of cycles. "A farm won't do you any good, because it's only going to run on one machine," Butts explains. "One machine with a conventional simulator will take quite a long time. It might take weeks just to get the system booted."