For static timing analysis, as with many other forms of analyses, there are tradeoffs to make between accuracy and speed. "For a truly dynamic environment with the highest possible degree of accuracy, you want to use Spice, but there are so many potential waveforms or settings you can use that it's impossible to perform all those analyses in our lifetime and sign off on a chip," says Silicon Metrics' Croix. So to accommodate dynamic effects in a static environment, it's best to use two tools—static and dynamic—in tandem.
The best tradeoffs of speed and accuracy imply a kind of filtering, in which designers apply the dynamic algorithms where they're needed to leverage accuracy, but then intelligently meld that data into static analysis to exploit its speed. "We have some interesting techniques for melding those things together into a flow," Croix says. Silicon Metrics is exploring the possibilities for a combination of methodology and software infrastructure that will allow engineers to take advantage of just enough dynamic analysis to set up highly efficient large-scale static analysis. They're much closer to the dynamic result, but they're much faster than running Spice on the whole thing.
Mentor Graphics' Carey Robertson agrees that signal-integrity analysis will require more dynamic-analysis solutions, along with accurate parasitic models. Robertson cautions that analysis can only be as good as the data being fed into it. This implies accurate and detailed parasitic information that explicitly report critical coupling information for dynamic analysis.
"As we move into smaller geometries, specifically 0.15 µm and below, the dominant contributor to delay is becoming the capacitance between the wires," says Bijan Kiani, vice president of marketing for Synopsys' Nanometer Analysis and Test. Synopsys' PrimeTime SI tool delivers both static timing analysis capability and static crosstalk analysis capability in an integrated solution that purports to address both problems.
Static analysis tools are inherently pessimistic, and dynamic tools are inherently optimistic, says Cadence's Scheffer. "Because pessimism is preferable to optimism—ask anyone who's ever had to recall a chip—static tools will prevail. That said, there's a lot of research into making static tools less pessimistic, and increasing the range of problems that they can attack, such as static prediction of peak supply currents without simulation," he says.
Many experts advise designers to carefully examine their SoC designs and attempt to find the truly critical nets. Then, it's suggested only those nets be subjected to thorough transistor-level dynamic simulation using Spice.
However, Rajiv Maheshwary, Synopsys' director of marketing for static timing products, warns that the onset of dynamic effects, like crosstalk, greatly complicates the process of determining just which nets in a design are "critical." "The world is changing with dynamic effects, and the problem will become less manageable for designers," he says.
Even if all modeling issues are ironed out, the problem of correct translation of modeling into actual silicon re-mains. According to Dale Pollek, vice president of marketing at Celestry Design Technologies, there's a growing need for process calibration, so that tools will provide analysis results that match processes and aren't simply theoretically accurate.
Plus, vendors like Numerical Technologies provide tools for analyzing optical effects that can make the world's most accurate modeling and analysis a moot point thanks to distortions that occur in silicon processes. According to Numerical's vice president of marketing, Michael Sanie, work is ongoing with leading parasitic extraction vendors to model layouts based not on idealized situations, but rather on simulated silicon images.