The Truth About Design For Manufacturing

"Magma's Blast Yield, Synopsys' IC Compiler, and Cadence's Encounter are all now capable of reading cell-yield information and optimizing yield as they do area, timing, and power," said Kevin MacLean, PDF's director of marketing. "We're taking the manufacturable information from a particular process and feeding it into the design flow."

A conversation with Nitin Deo, director of marketing at Ponte Solutions, centered on another approach to a modelbased DFM paradigm. "Any change that has to happen after layout and in GDSII is too late," said Deo. Ponte's technology is a model-based approach that relies on yield analysis during the design stage.

Three applications emerge for the yield-analysis approach. One is during the design of cell libraries and IP. "Right from the start, you ought to be able to analyze libraries just like for timing and power and have different yield numbers available for different cells," said Deo.

Once characterized libraries and IP are used to build a netlist, that netlist is analyzed for factors that will cause yield loss. Designers have two options: swap out problem cells, or change those cells' layouts for improved yields.

The third use is full-chip analysis after detailed routing. This is still the pre-GDSII realm, but a point at which major contributors to yield loss can be ferreted out and put in check.

For Silicon Dimensions, whose Chip2Nite tool endeavors to move physical-design information farther into the front end of the process, DFM is not so much addressing problems early in design as it is avoiding them in the first place.

"The first thing is the wires," said Michael Munsey, Silicon Dimensions' director of marketing. "We always try to minimize wire lengths. At first, we did that for timing reasons. But if you minimize lengths, you have less chance for lithography problems."

Vias are another area in which problems can be avoided, and addressing wire lengths makes a difference. "Via counts have been rising even faster than die sizes," said Munsey. "The reason is because the wire length is going up. So less wires also means fewer vias, which also means less chance of yield issues."

A FOUNDRY'S POV
Having finally encountered some healthy discussion of tools and techniques for improving yields, I returned to a final talk with TSMC's Chuck Byers. That conversation was joined by Bill Hara, vice president of engineering and technology at Altera.

"Almost by definition, the foundry 'design-for' rules are guidelines. As such, it's very difficult to follow them," said Hara. "They are in a gray area between what absolutely must be done and what would be good practice."

The answer, say TSMC and Altera, is collaboration. "The foundry and IC maker must work together to decide why these rules were created and what the costs are," said Hara.

Just as important, if not more so, is collaboration between foundries and EDA tool vendors. "Libraries, IP, and process design kits (PDKs) play a role in the overall DFM paradigm," said Byers. "There must be collaboration with the EDA vendors. Our in-house libraries must be aware of the rules and recommendations. We're cooperating with the EDA vendors in aligning PDKs with manufacturing guidelines."

Having looked high and low for the spirit if not the letter of the law of true design for manufacturing, I can only conclude that it's a developing area. Rule-driven DFM must, over time, be shunted aside in favor of a model-based paradigm. To engineers facing a 90-nm tapeout, I can only advise caution in the face of marketing pitches. Look hard for true DFM. It's out there, at least in nascent form.