In design automation, as in other areas of the electronics industry, technologies and methodologies find broad acceptance through standardization. For example, the standardization of the Verilog hardware description language made RTL synthesis viable in the mid-1980s.
In the verification realm, new and emerging standards are behind the broadening acceptance of transaction-based verification methodologies. Standards like OSCI’s TLM (transaction-level modeling) 2.0 and Accellera’s Standard Co-Emulation Modeling Interface (SCE-MI) have led to a groundswell of interest in transactions. Also, flows are now using hardware acceleration and emulation to give transaction-based verification a turbo boost in speed.
Why Use Transactions?
In modeling system designs, there are usually three goals to be achieved, says Ran Avinun, group director of system design and verification product management at Cadence Design Systems. “One is early software development, a second is early system definition, and a third is description of executable specification, which you want initially for architectural tradeoffs,” Avinun says.
Where do transactions fit in, and why would a designer want to start from transaction-level models and eventually move those models into hardware acceleration? For many users, the answer lies in much faster simulation. “If you write models as TLMs, or you communicate through transaction-based verification, simulation runs faster,” says Avinun.
Another benefit of using TLMs is faster and easier debugging. “In general, if you write TLMs, you generate fewer bugs and spend less time debugging problems. It also gives you an opportunity to distinguish between functionality and implementation,” says Avinun.
“You want to write a model that represents functionality, and then separate the constraints. Those can be clocking constraints, or process node-specific things that might change over time. It’s easier to reuse models as you move from application to application or node to node,” Avinun says.
How Transactions Are Used
At least five use models have become predominant when it comes to TLMs, according to Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys (see the table). At the top of the list is a reuse scenario.
In such cases, you would already have a good deal of your design in RTL. Here, the best solution is a mixed-mode simulation methodology in which the existing RTL is run on FPGAs. Meanwhile, TLMs for new blocks within the design are run as a virtual prototype.
Second on the list is a verification use model. In this scenario, you start with a testbench and then develop a virtual prototype before you have RTL available. This is accomplished with untimed TLMs.
“People start with untimed models to define the verification scenarios they want to cover,” says Schirrmeister. “Can my phone receive a call while I play a game and download something? You can easily define those early on with the virtual platform because they are in software running on the processor. You then use them later on in the project.”
A third use model is in evaluating the connections between the system and the outside world. These connections can be in the form of physical or virtual I/O.
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