There's support for phase tolerance measurements for clocks, and the software differential pairs and handles complex power measurements accounting for pin currents and all defined voltage sources. It can describe arbitrarily complex load structures, including RLC modeling for solder junctions, bond wires, and leadframes. It also handles driver conditions, including ideal, emulated, and full active drivers and their connection networks.
Hulett says it's this ability to characterize I/Os in context that makes the tool shine. "If, for example, you had four I/Os all sharing one power-ground pad, you could evaluate how the inductance of the power supply impacts the characteristics of the I/O," he explains.
During characterization, the design team essentially creates an arbitrary network that reflects the I/O pad's context. The tool derives this network from an I/O functional description, an extracted netlist, and process models.
Meanwhile, the tool's I/O Methodology Compiler uses a behavioral description of the cell to extract all the measurements relevant to a digital model that can be used in a full chip timing or power analysis tool. This is done using a binary decision diagram-based arc extraction engine that uses the electrical specification of a cell to create packaged tests much like the packaged tests generated by a specification compiler.
The I/O Methodology Compiler lends itself to interfacing the tool to a variety of commercial and proprietary simulators, including SmartSpice, Star-HSpice, and Spectre (available in this quarter). SiliconSmart IO also features a graphical user interface and shell-based batch mode interface. Built for use in a .tcl environment, the tool can be driven by custom command structures to let users instantiate models in various tool flows.
Virtually any kind of I/O can be characterized and have models automatically generated. Some designers work with custom I/Os that do not necessarily conform to a published specification. Over the next two quarters, the tool will be incrementally upgraded to validate what Rao calls design compliance rather than specification compliance. The intention is to apply the same programmatic constructs the tool uses internally to build specification compliance packages for internal specifications.
Support is built in for complex I/O port specifications, including differential ports, voltage- and current-referenced ports, and analog ports. There's complete functional support for bi-directional cells, arbitrarily complex sequential functions, illegal paths and states, and digital, nondigital, and analog functions. The tool also can handle cells of arbitrary size and is limited only by the capacity of the target simulator. Multiple strength pads in the context of SSTL will be supported in the next major revision, expected in Q4 of 2002.
Once characterized, models must be published. Currently, the tool supports Synopsys .lib (Liberty) models for timing and power. According to Rao, Silicon Metrics will add Verilog and IBIS over the next quarter, to be followed by other model formats like ALF and TLF.
Price & Availability
Pricing for SiliconSmart IO is modular. However, an entry-level package starts at $90,000. The tool is available now with support for Solaris and HP-UX platforms, with Linux support coming later this year. Electrical specification compliance validation will be available for LVDS, SSTL, and I2C in the current quarter. USB 2.0, PCI, PCI-X, and AGP will be available in the fourth quarter.
Silicon Metrics Corp., 12710 Research Blvd., Suite 300, Austin, TX 78759; (512) 651-1500; www.siliconmetrics.com.