Hier's silicon virtual prototyping capability goes beyond partitioning and adding area constraints to ensure that partitioning results in more connectivity within blocks than between blocks. The opposite scenario, says Raje, defeats the purpose of partitioning and it might as well be placed and routed flat.
The PlanAhead tool, which sells for $25,000 for a one-year time-based license, is available now. Supported platforms include Sun Solaris 5.8, Linux 7.3, and Windows XP.
Not all FPGA vendors are sold on the concept of silicon virtual prototyping, though. "If you have a well designed, high-performance device architecture, there is no need for this kind of tool for most designs," says Tim Southgate, Altera's VP of software and tools marketing. "However, for those difficult designs, it can be helpful to make use of floorplanning and physical synthesis."
Altera provides established FPGA synthesis vendors with its device architecture data. As a result, the vendors can optimize their tools for placement-based physical synthesis and shorten the synthesis placement iterative cycle. But the challenge for EDA vendors is that this capability is unique to each FPGA architecture, so it requires a large effort to develop physical synthesis support.
For its part, says Actel's Kish, Actel will introduce floorplanning technology in its next-generation integrated design environment. This new feature will aid logic placement, I/O assignment, and routing to achieve the best tradeoffs between achieving optimal design density and performance.
Other vendors have pushed to beef up their FPGA flows to handle the larger devices. Mentor Graphics has announced a three-part flow extending from high-level design through the programmed part's interface to the pc board.
"We believe that design of complex FPGAs is not just synthesis and place and route anymore, which is currently a mainstream design flow," says Simon Bloch, Mentor's general manager for FPGA design. Issues like multiple clock domains complicate matters, as does complexity itself. "We're seeing place-and-route cycles for 6-million-gate devices taking 24 hours. If the engineers do 50 iterations, which is not unusual for devices this large, the resulting design cycle begins to look like that of a small ASIC," he continues.
Mentor's answer is a flow that spans design and verification for the FPGA itself, the embedded system it's part of, and the pc board(s) that carry that system. The flow comprises existing tools, such as the HDL Designer tool suite, the Precision RTL synthesis tool, ModelSim for HDL simulation, and Seamless for hardware/software co-verification. They'll be augmented, in time, with other offerings in areas such as high-level synthesis and, possibly, formal verification. Mentor also will work to tie generic tools, such as Platform Express, Seamless, and its software-development tools like Nucleus, CodeLab, and the XRay debugger, to specific FPGA devices.
Also taking a high-level approach to FPGA design is Celoxica, which recently announced support for the 90-nm version of Xilinx's Spartan3 devices. Celoxica's DK Design Suite provides a C-based language design environment that enables partitioning of designs between hardware and software. It offers seamless verification of the system at the architectural level and direct synthesis from C-based models. Celoxica's methodology supports C, C++, SystemC, and Handel-C.
While Mentor contemplates high-level FPGA synthesis, it's already arrived in the form of AccelChip's AccelFPGA tool. Version 2.0 of the tool, which automatically generates synthesizable RTL models directly from Matlab, carries enhancements that boost DSP developers' ability to synthesize Matlab designs. DSP developers are freed from using Matlab designs as specifications for driving manual RTL modeling. New in version 2.0 is automated support for conversion from floating-point to fixed-point representations, as well as support for automatic import of foreign models. This paves the way for a new library of DSP IP, called AccelWare, for release in the third quarter.
Full FPGA tool suites don't always have to target the highest-end devices, though. In its Board-on-Chip technology rollout, Altium targets the Xilinx Spartan and Altera Cyclone devices, preferring to call these "low-cost system FPGAs."
Like Mentor, Altium's flow is a system-level approach with several main thrusts. First is a capture environment for system-level design based on the nVisage schematic-entry package, which enables mixed schematic-level and HDL design. Altium's approach to IP is a critical element here.
"An important part of the technology is the ability to supply high-level components in a pre-packaged, pre-synthesized form," says Rob Irwin, Altium's manager for brand strategy. "So we'd supply soft cores. Also a range of peripherals and analogous components to say, muxes, logic devices, that sort of thing."
A third component of Altium's flow is to provide reconfigurable hardware development platforms. The NanoBoard breadboards will eventually broaden into an application-specific line for various kinds of design work. Last is a comprehensive approach to software development, embodied in the Tasking products.
FPGA vendors themselves continue to improve both their hardware and software offerings. This is exemplified in Altera's HardCopy Stratix mask-programmed devices and Quartus II version 3.0 design software (see "Hardwired FPGA Option Shrinks Chip Size And Cost," Electronic Design, July 21, 2003, p. 34, ED Online 5318). The HardCopy Stratix parts offer up to 100% performance gains over the Stratix FPGAs, while lowering power consumption and per-part costs compared with the earlier HardCopy APEX devices.
The new Quartus II release lets designers directly target HardCopy Stratix devices from the beginning of the development cycle, rather than doing development work on FPGAs first and then moving the design over to the HardCopy platform. The software delivers design performance metrics for these devices as early in the cycle as it does for FPGAs. Designers can assess speed performance, power consumption, logic-cell placement, and I/O assignments before implementation, an essential capability for system-level board design.