In either case, partitions are created within the design, according to Jordon Inkeles, Altera’s senior manager for software product marketing. “Partitioning is similar to what an architect does on a white board at the outset of a design project, dividing up the design among individuals by functions,” says Inkeles.
In the top-down flow, you divide it up into blocks A, B, and C (Fig. 2). The entire design stays within the same Quartus project. When a change is made to partition A, the team can lock partitions B and C, maintaining timing in those partitions and reducing overall compilation time by up to 70%.
The bottom-up flow is a team-based variation. In this case, the partitions are divided into separate Quartus projects. “Partitioning for a bottom-up flow would be done by the system architect up front inside Quartus,” says Inkeles. Once the partitions are within separate Quartus projects, different individuals or teams can work on them in parallel and in different locations.
Similarly, Xilinx has made progressive improvements to its tool flow. “From a tool standpoint, we looked at things like language support,” says Bruce Fienberg, Xilinx’s senior group communications manager for products and solutions. “We had to make sure the language support designers had in ASIC tools was the same here. We revamped the tools so that we’re at parity with the rest of the industry.”
In Xilinx’s most recent tool release, ISE 11.1, the company rethought its approach to customers as well as how it delivers its technology. “We’ve said for years that FPGAs are good for embedded applications and DSP. But these designers tend to not be FPGA people, so the goal is to make the technology easier for them to access,” says Fienberg.
Xilinx came up with four interoperable and domain-specific design flows and tool configurations for logic, DSP, embedded processing, and system-level design (Fig. 3). “Think of a pyramid, a base platform which is the tools, the IP, and the silicon for basic logic design. The next level is the domainspecific platforms. There we add reference designs and kits for those various domains,” Fienberg continues.
“As we move toward 2010, we’ll deliver market-specific targeted design platforms in which we build on a base and domain to create very application-specific solutions. Examples might include a video development kit or industrial-control development kit. The idea is to not assume that because someone is an EE that they can design an FPGA,” says Fienberg.
NEW KID ON THE BLOCK
Every so often, new FPGA vendors appear with silicon that attempts to put a twist on what’s come before. An example is Achronix Semiconductor Corp., which touts its FPGAs as the world’s fastest.
“Traditional FPGAs have decent speed at the I/Os but fall short in speed of the fabric,” says Yousef Khalilollahi, Achronix’s vice president of worldwide sales and marketing. “This means that customers have to compromise performance inside the device. Our value proposition is not only high-speed I/O, but we keep the speed throughout the fabric of the FPGA. To quantify that, our devices achieve up to 1.5-GHz peak performance.”
To complement its silicon, like other FPGA vendors, Achronix offers its Achronix CAD Environment (ACE) suite of software for implementation. “The design flow that customers use for our FPGAs is the same as for any other device,” says Khalilollahi. “We use standard Verilog and VHDL as design entry. That code is run through synthesis, which is shipped by us and is either Synopsys’ Synplify Pro or Mentor Graphics’ Precision Synthesis.”
The output of the synthesis tool is entered into the ACE back-end tools. Within the ACE environment are five different views of a design project. The Projects View is the default view with a hierarchical view of the workspace. Here, users create projects and can view netlists, constraint files, and IP.
A second view is IP Configuration, which automatically generates complex IP and creates the RTL as users specify, as well as generates the associated constraint files. A third view, Physical Layout, provides a graphical view of the device’s physical layout, allowing users to visualize place-and-route data as well as critical paths. Here, cross-probing is enabled between timing analysis and layout.
With the Package Viewer, users can visualize the device’s package and assign pins. They’re able to see banks of I/Os and their associations and ensure that buses are grouped together in a way that makes sense. The fifth and final view, Debugging, comes into play after the user programs an FPGA with a bitstream. In this view, the user can set up logic within the design with which to capture a trace buffer.