The next TDD step follows the design into the spatial-filter block. But before descending into this block, let's zoom into its instantiation on this level (Fig. 4). Now there's a clearer picture of the symbol graphics and more hierarchical techniques in use. These include arrows to indicate the direction of data flow, and cross-reference page numbers in the symbol to help the reader navigate when using paper plots.
Descending into the spatial-filter instance reveals the spatial-filter schematic. Again, true to TDD, this schematic is built of a manageable number of blocks. For the first time, though, some primitive blocks for this pc-board design are visible. Zooming into the top of this schematic sheet reveals the first of the board-level components (Fig. 5).
Notice the use of additional hierarchical design techniques for board-level components, which include bus pins, along with condensed pin numbers and labels. In this case, many of the pin numbers are sequential, so they can be described in a compact form. If the numbers were less compact, the labels and pin numbers could be replaced by aliases and represented in detail in an automatically generated table near the symbol, or on a second sheet. In the actual application, the line buffers and other board-level components were modeled in VHDL, but verification at this level was deferred until the completion of the FPGA design.
Descending further into the spatial- filter FPGA reveals an assembly of synthesizeable blocks provided by the FPGA vendor (Fig. 6). These blocks include simulation models that allow the FPGA to be simulated either alone or in a system using Mentor's ModelSim digital simulator. Having reached a primitive for a pc-board design, the design of this branch is now complete.
Identical TDD techniques were employed on all other branches of the design, until the entire design was complete. At this point, all components were completely modeled, allowing simulation at any level, including a complete board-level simulation.
The finished pc board consisted of 14 custom FPGAs, four hardware multipliers, 18 line memories, 10 static RAMs, and miscellaneous buffers and glue logic. Al-though the modeling and simulation delayed the layout and fabrication by several weeks, many months were saved in the post-fabrication bench testing. In fact, using HTDD and board-level simulation, the entire temporal-filter board was fully tested, in all its dozens of modes of operation, within two weeks of its first fabrication.
The authors would like to thank Camtronics Medical Systems (www.camtronics.com) based in Hartland, Wis., for providing information on the image processor described in this article.
Gary Pratt is a technical marketing manager for the analog/mixed-signal product group of Mentor Graphics Corp. (www.mentor.com), headquartered in Wilsonville, Ore. He holds a BSEE from the University of Wisconsin, Madison. Pratt has practiced as a licensed professional engineer for 18 years, and he has been an enthusiastic proponent of EDA tools since 1982. He can be contacted by phone at (262) 369-5394, or via e-mail at gary_pratt@mentor.com.
Jay Jarrett is a product marketing manager for Mentor's systems design division. Since 1986, he has worked in the EDA industry in various technical and management roles focusing on design entry, digital simulation, and system integration. Prior to 1986, Jarrett was the lead engineer for ASIC development at a leading telecom manufacturer and a systems integrator for a major defense contractor. His e-mail address is jay_jarrett@mentor.com.
The next TDD step follows the design into the spatial-filter block. But before descending into this block, let's zoom into its instantiation on this level (Fig. 4). Now there's a clearer picture of the symbol graphics and more hierarchical techniques in use. These include arrows to indicate the direction of data flow, and cross-reference page numbers in the symbol to help the reader navigate when using paper plots.
Descending into the spatial-filter instance reveals the spatial-filter schematic. Again, true to TDD, this schematic is built of a manageable number of blocks. For the first time, though, some primitive blocks for this pc-board design are visible. Zooming into the top of this schematic sheet reveals the first of the board-level components (Fig. 5).
Notice the use of additional hierarchical design techniques for board-level components, which include bus pins, along with condensed pin numbers and labels. In this case, many of the pin numbers are sequential, so they can be described in a compact form. If the numbers were less compact, the labels and pin numbers could be replaced by aliases and represented in detail in an automatically generated table near the symbol, or on a second sheet. In the actual application, the line buffers and other board-level components were modeled in VHDL, but verification at this level was deferred until the completion of the FPGA design.
Descending further into the spatial- filter FPGA reveals an assembly of synthesizeable blocks provided by the FPGA vendor (Fig. 6). These blocks include simulation models that allow the FPGA to be simulated either alone or in a system using Mentor's ModelSim digital simulator. Having reached a primitive for a pc-board design, the design of this branch is now complete.
Identical TDD techniques were employed on all other branches of the design, until the entire design was complete. At this point, all components were completely modeled, allowing simulation at any level, including a complete board-level simulation.
The finished pc board consisted of 14 custom FPGAs, four hardware multipliers, 18 line memories, 10 static RAMs, and miscellaneous buffers and glue logic. Al-though the modeling and simulation delayed the layout and fabrication by several weeks, many months were saved in the post-fabrication bench testing. In fact, using HTDD and board-level simulation, the entire temporal-filter board was fully tested, in all its dozens of modes of operation, within two weeks of its first fabrication.
The authors would like to thank Camtronics Medical Systems (www.camtronics.com) based in Hartland, Wis., for providing information on the image processor described in this article.
Gary Pratt is a technical marketing manager for the analog/mixed-signal product group of Mentor Graphics Corp. (www.mentor.com), headquartered in Wilsonville, Ore. He holds a BSEE from the University of Wisconsin, Madison. Pratt has practiced as a licensed professional engineer for 18 years, and he has been an enthusiastic proponent of EDA tools since 1982. He can be contacted by phone at (262) 369-5394, or via e-mail at gary_pratt@mentor.com.
Jay Jarrett is a product marketing manager for Mentor's systems design division. Since 1986, he has worked in the EDA industry in various technical and management roles focusing on design entry, digital simulation, and system integration. Prior to 1986, Jarrett was the lead engineer for ASIC development at a leading telecom manufacturer and a systems integrator for a major defense contractor. His e-mail address is jay_jarrett@mentor.com.