BACK-END DESIGN AND ANALYSIS
Augmenting its existing RTL-to-GDSII flow, Magma will show its new Blast Rail product for power integrity in nanometer IC designs. The tool simplifies power-rail design by combining power planning, power analysis, voltage-drop analysis, voltage-drop-induced delay analysis, and analysis of electromigration on rail wires and vias. Built with Magma's unified data model architecture, Blast Rail offers instant access to analysis data for on-the-fly corrections that avoid post-route iterations.
As IC manufacturing technology continues its march into the nanometer realm, so goes the cost of IC manufacturing. Current predictions have the cost of a mask set at 90 nm rising to $2 million. The cost of computing infrastructure capable of designing and verifying ICs is rising significantly as well. Mentor Graphics will roll out Calibre MTFlex, a next-generation extension to Calibre's current hierarchical data-processing engine (Fig. 2). The extension will enable the design-to-silicon tool suite to perform highly scalable, multi-threaded data processing in price-conscious distributed compute environments.
As always, design verification will be a hot topic at DAC. Assertion-based verification will be among the major trends emerging at the show. Assertions express expected design behavior and drive the emerging verification tools that use them to improve the quality of design validation. Driven by increasing complexity, assertion standards are shaping up, largely due to the efforts of Accellera. Formal-verification tools are improving as well. Some simulators now support assertions, giving designers even more reason to at least look into using them.
Novas will demonstrate the latest version of its Verdi behavior-based debug system with support for assertions. Assertions accelerate the ability of the debugging process to locate and isolate the causes for design behavior. Browsing and tracing tools are used to apply familiar debug techniques to assertions, allowing users to view assertion source code annotated with values produced by simulators and formal tools. They can also trace from assertion source directly to the HDL source code. Results of assertion evaluations can be seen in a waveform display, including trigger times and pass/fail results.
On the formal verification front, Real Intent will show version 4.0 of its Verix formal tool. Verix 4.0 delivers multimillion-gate capacity for formal assertion verification. It includes over 14 classes of automatic assertions, as well as a Verilog/VHDL-like assertion language that permits users to define their own assertions with a minimal learning curve.
The tool supports Accellera Open Verification Library (OVL) assertions, allowing users to apply formal analysis to verify behaviors expressed in OVL. Designers can plug-and-play OVL assertions between Verix and a simulator to perform formal and dynamic analysis (Fig. 3).
Putting the "formal" in formal verification, of course, is the notion of an exhaustive analysis of all possible test vectors. At DAC, 0-In Design Automation will announce the industry's first formal-verification metric that links simulation with formal-verification effectiveness. The result is a comprehensive measure of how well designers have verified their ASICs, SoCs, and custom ICs. With the unified metric, users will be able to identify verification holes in both simulation and formal verification. The metric highlights parts of the design that haven't received sufficient functional coverage in the context of a verification test plan.
Hardware-verification systems have sorely needed a capacity boost. Emulation and Verification Engineering (EVE) is debuting a multiboard system that extends the capacity of designs to 12 million ASIC-equivalent gates from 1.5 million gates in the previous version. The ZeBu platform accelerates the verification process of FPGA-based designs as well as the software-development cycle for embedded systems. Up to eight ZeBu boards can be connected together to accommodate designs ranging from 1 million to 12 million ASIC-equivalent gates. Thanks to EVE's Z-EmuNet networking technology, multiple boards can be installed in multiple PCs for use collectively on one large design or individually and concurrently on smaller designs. Pricing starts at $49,000 for a 1 million-gate system.