Meeting time-to-market windows and finding ways to improve the profitability of new products is not only important, but a matter of survival, especially given the current economic conditions and market instability. With cost-cutting measures in place at most high-technology electronics companies, all aspects of the design, verification, and manufacturing process are under scrutiny for ways to improve productivity and reduce cost.
Not least among them is the manufacturing test and design-for-test (DFT) process. New test solutions, such as embedded deterministic test (EDT), reduce test data volumes and test times by up to a factor of 10 and can dramatically contribute to reducing overall test costs. But what about time-to-market? How can system-on-a-chip (SoC) engineers make the best use of DFT methodologies to ensure that they meet design schedules while improving test quality?
The foundation for any structured DFT methodology is scan design. Scan lets the large sequential functions implemented in a design be partitioned into small combinational blocks during test. Scan is the standard DFT infrastructure for delivering test data to internal nodes of the circuit and for observing their responses. With today's multimillion-gate SoC designs, scan is required to ensure efficient generation of high-quality manufacturing tests.
Indeed, scan is considered the basic building block for automating the entire test-generation process. Assuming that scan is a given, let's look at what other test-related structures are needed in SoC designs, and where automation can improve the process.
Structurally, today's SoCs are not much different from those developed several years ago. The big difference is that they're faster with more and smaller transistors. As far as testing the internal structures of the device is concerned, the process can be separated into two basic areas: logic and memory.
Testing Logic: Scan and automatic test-pattern generation (ATPG) are the solutions of choice for ensuring the highest-quality test during manufacturing. Functional test strategies are losing popularity across the industry due to their high development cost. It has also become difficult, if not impossible, to grade the effectiveness of functional tests for large multimillion-gate designs. The simplicity and effectiveness of ATPG and scan-based test patterns directly address the problems of functional test patterns and offer several advantages.
Functional testing implies that tests are only delivered through functional operation of the device (Fig. 1a). Thus, it doesn't make use of scan to deliver tests to internal nodes of the device. Instead, functional testing relies on testing internal nodes by delivering stimulus through the external pins of the device and clocking the device as it would be under normal operation.
Generating this type of test for a large design, and ensuring that the entire design is adequately tested, requires extensive manual effort as well as in-depth knowledge of the design and its operation. One can envision the problems and effort required to test some small block of logic within a 5 million-gate design. In many cases, this takes thousands of clock cycles and primary input sequences just to get the right test data to that embedded block. The designer must then figure out how to get the data back out to primary output pins to observe a potential failure.
On the other hand, using scan-based test patterns provides access to internal nodes of the design and simplifies the problem into much smaller blocks of logic (Fig. 1b). Additionally, scan and ATPG enable the entire process of generating the test patterns to be fully automated. This ensures very high coverage in test patterns, as well as a predictable and repeatable process. Today, ATPG tools can generate very high-coverage test patterns for multimillion-gate designs in a matter of hours.
Basically, ATPG has become the standard for generating tests to detect static defects (or stuck-at failures). But as device sizes shrink, testing for static failures alone may not be sufficient. The higher performance and increased levels of integration found in SoC designs are now leading to new types of failure mechanisms—and the need for new types of test. The microprocessor industry, where performance is critical, has led the way in "at-speed" testing. But now, even standard IC processes moving to 0.13 µm and below are supplementing standard "stuck-at" patterns with "at-speed" tests.