Baseband communications dataplane
processing is one of the most demanding
environments around. Tensilica’s ConnX
Baseband Engine is designed to address
this challenge (see the figure). Tensilica calls
its architecture a dataplane processing unit
(DPU), in contrast with CPUs and DSPs.
The processor cores are based on Tensilica’s
Extensa LX. The system includes
one scalar core plus eight SIMD cores. Verylong-
instruction-word (VLIW) instructions
control the scalar core plus an eight-way dual
ALU engine and SIMD engine. The system is
fed by 160-bit registers and a pair of 128-bit
memory interfaces. It can mange up to eight
vector divides and two square roots or four
complex FIR taps or radix-2 and radix-4 butterfly
operations/cycle. Also, it can perform
16 18-bit MAC operations/cycle.
Tensilica delivers custom configurations,
so the base system is just the starting point.
Options include multiple queue ports and
160-bit FIFOs via the SIMD vector registers.
The processor interface can be linked to an
AMBA bus, providing access to a wide range
of peripheral IP. Connections can use a crossbar
switch or bus. It can support multiple
memory interfaces as well.
TENSILICA
www.tensilica.com