High Address Latch Disabled
The ALE signal generated by the CPU is gated off by the multiplexer chip to permit the PIC to load the address latches. (Both latches are loaded with the same value, but the high address latch is disabled.) The write-enable pins of the high and low RAM chips, which are driven in common when the CPU is writing to RAM, are separated to allow the PIC to write bytes to the RAM chips individually. If the main processor has an 8-bit data bus, however, things are much simpler.
Figure 2 shows the complete loader circuit, apart from the 8-pin, 10-kΩ SIP that pulls up address bits 9 through 15 when the address latch is disabled. An earlier implementation of this loader used three-state drivers to control the RAM. The drivers and the PIC output pins were connected in parallel to the RAM chips. Using a multiplexer chip eliminated an inverter.
When loading code, the PIC outputs an 8-bit address and writes it to the address latches (see the code listing). Next, it fetches an instruction byte from its EPROM, puts it on the bus, and sends a memory write pulse to the high or low RAM chip as appropriate. It repeats these operations sequentially until it has transferred as many bytes as are needed. Then it turns the main processor on and goes to sleep, consuming negligible power.
It's undesirable for the main processor to be turned on before there is code ready for it to execute. The circuit then has to allow for the PIC's built-in power-on delay, which can be as long as 30 ms. Initially, an RC reset signal some 100 ms long holds the processor off the bus. As soon as the PIC starts up, it generates an overriding reset. After that, it loads the bootstrap code and waits 100 ms to make sure that the RC circuit has timed out before it releases its reset.
Driving The Master Clock
The PIC can run from any convenient clock of up to 20 MHz. In my system, I used the PIC to drive the master clock crystal, saving the space taken by a crystal oscillator. If you do this, you must end the loader program with an endless loop since putting the PIC in sleep mode stops its clock.
In a word-addressed system, the low address latch normally stores address bits 1 through 8. Bit 0 isn't needed because it only serves to distinguish the high and low halves of a word when reading bytes. The two write-enable strobes in this circuit serve that function. When the microcontroller writes an address byte to the latch, bits 1 through 7 of the address appear in their normal positions in the byte. The same byte appears on both the high and low halves of the bus, so bit 8 of the address must be placed in the bit 0 position of the byte.
One peculiarity of the smaller PIC chips is their mechanism for storing data in their program EPROM. Data bytes are encoded as one of 256 different return instructions. To implement a lookup table, a subroutine call must be made to a calculated address. The number embedded in the return instruction at that address is loaded into the working register. Table addresses have eight bits. The ninth bit is zero, and as a result, the table must be located in the first 256 words of the chip's 512-word program memory.
Another oddity of the 16C5x series is that these models start execution at their highest memory address. This is a nuisance when programming the chip. The PIC's EPROM is loaded sequentially, making it important to pad all programs to exactly 512 instructions. If the unused program area is left unprogrammed, the chip will execute a dummy instruction on startup and roll over to address zero.
I once got into trouble when I put a copyright notice into the last few code words. The first thing the chip executed was a return instruction. If a chip happened to power up with nonzero return-stack contents, the program crashed. I mention this because the listing shows GOTO START as the first instruction, whereas ideally it should be instruction 511. The indirect subroutine call must lie within the first 256 instructions. That's why I put it immediately after GOTO START.
Since the first two table entries indicate the loading address in RAM and the number of words to be loaded, only 252 entries—126 words—are available for the bootstrap program itself. The count represents the number of 16-bit words to be loaded, so the table must be padded to have an even number of bytes. Similarly, the loading address must be even.
If some 250 bytes of bootstrap code aren't enough, the 16C56 can be substituted for the 16C54. The 16C56 has 1024 locations for storing instructions, of which 512 instructions can be data table bytes. The loading program must be changed to select the appropriate table.