Topology Considerations
The key topologies of the ATCA specification are Dual-Star, Dual Dual-Star, and Mesh. Naturally, the topology can have a great impact on overall system cost because the cards, backplane, and so forth, will be affected. For example, a Mesh topology can demand significantly more layers than a Dual-Star topology. With more point-to-point links, more layers must be added to achieve the signal routing. Therefore, Mesh topologies are often implemented in smaller systems (frequently in a horizontal-chassis configuration) where one can achieve high performance in less space.
In the PICMG 3.0 specification, the pc-board design has recommended values to ensure proper functionality over FR4 material. For example, the maximum backplane thickness is 6.35 mm, with no more than a 533-mm trace length. Although the design values are stringent, there are creative ways to ensure an optimal design. An experienced designer can improve the performance and reliability of the backplane, often cutting down the number of layers used and reducing costs. For example, in a Dual-Star or Dual Dual-Star configuration, the physical position of the hub slots on the backplane isn’t restricted. The position of the hub slots is critical because it will determine the maximum trace length on the backplane.
Bustronic and TreNew, backplane subsidiary divisions of Elma, hypothesized that placing the hub slots in the center of the backplane, could reduce the trace lengths and number of layers. To prove this, we performed simulation on a 14-slot Dual-Star configuration. The results showed that the maximum trace length could be cut in half. In turn, there was vast improvement in signal quality as the losses due to dielectric and skin effect were considerably smaller. The maximum trace length would be about 270 mm. Further, by placing the hub slots in the middle, intelligent routing solutions were implemented. This reduced the number of layers from 18 to only 12. Besides reducing cost, the smaller number of layers leads to a pc-board thickness of 3.2 mm, minimizing the stub influence and improving the signal quality.
Figure 4a shows a TDR profile for the worst-case stub. It represents a trace situated in the first signal layer under the connectors. The minimum differential impedance is only 85 ½. One may also notice that the measured backplane impedance is about 102 Ω. This very small tolerance of only 2 Ω results from strict conditions worked out using reliable and quality pc-board manufacturers. Measurements were performed using passive and active cards with real drivers that operate at 3.125 Gbits/s. The traces on the cards are 5 mils wide and 115 mm long. Figure 4b shows the eye diagram for the longest trace on the backplane situated in the worst-case layer.
The eye opening is about 509 mV—a strong result considering that the driver used for measurement requires at least a 200-mV opening. In a live system, performance is expected to be even better because additional noise introduced by the measurement cables and SMA contacts would be eliminated. Using standard FR-4 material wasn’t a problem. Employing various transceivers and SerDes devices, simulation and performance measurements showed that speeds of over 5 Gbits/s were reliable using FR4.
A good ATCA backplane design will consider issues such as hub slot placement, trace lengths, and intelligent routing strategy to optimize layer count and reduce costs. Further, these backplanes should be designed with plugging considerations in mind whereby shelf managers, fan trays, and headers receive signals from other Intelligent Platform Management Interface (IPMI)-enabled devices, etc.
Shelf Management
Shelf management is a critical element in carrier-grade computing platforms. Lately, shelf managers developed for the PICMG 3.0 specification use the IPMI. To maximize efficiency, one can incorporate a shelf manager that individually controls the fans in the chassis. Figure 1 also shows the shelf managers incorporated in a 5U ATCA unit.
For redundancy, another important issue in carrier-class systems, the shelf manager can be designed as dual units in a hot-swap redundant mode. It would support redundant operation with an automatic switchover, where one shelf manager will be active, while the other is a backup unit.
Finally, an interface board can be used for direct shelf-manager plugging. The interface board can be located either inside or outside of the ATCA card cage, offering great flexibility in design.
Developing a chassis that meets specific customer needs can be challenging for any specification, let alone a new one like ATCA. However, by adopting a step-by-step design methodology and using a comprehensive specification such as PICMG 3.0 for ATCA, it can be a springboard for the successful development of a CGOS.
Topology Considerations
The key topologies of the ATCA specification are Dual-Star, Dual Dual-Star, and Mesh. Naturally, the topology can have a great impact on overall system cost because the cards, backplane, and so forth, will be affected. For example, a Mesh topology can demand significantly more layers than a Dual-Star topology. With more point-to-point links, more layers must be added to achieve the signal routing. Therefore, Mesh topologies are often implemented in smaller systems (frequently in a horizontal-chassis configuration) where one can achieve high performance in less space.
In the PICMG 3.0 specification, the pc-board design has recommended values to ensure proper functionality over FR4 material. For example, the maximum backplane thickness is 6.35 mm, with no more than a 533-mm trace length. Although the design values are stringent, there are creative ways to ensure an optimal design. An experienced designer can improve the performance and reliability of the backplane, often cutting down the number of layers used and reducing costs. For example, in a Dual-Star or Dual Dual-Star configuration, the physical position of the hub slots on the backplane isn’t restricted. The position of the hub slots is critical because it will determine the maximum trace length on the backplane.
Bustronic and TreNew, backplane subsidiary divisions of Elma, hypothesized that placing the hub slots in the center of the backplane, could reduce the trace lengths and number of layers. To prove this, we performed simulation on a 14-slot Dual-Star configuration. The results showed that the maximum trace length could be cut in half. In turn, there was vast improvement in signal quality as the losses due to dielectric and skin effect were considerably smaller. The maximum trace length would be about 270 mm. Further, by placing the hub slots in the middle, intelligent routing solutions were implemented. This reduced the number of layers from 18 to only 12. Besides reducing cost, the smaller number of layers leads to a pc-board thickness of 3.2 mm, minimizing the stub influence and improving the signal quality.
Figure 4a shows a TDR profile for the worst-case stub. It represents a trace situated in the first signal layer under the connectors. The minimum differential impedance is only 85 ½. One may also notice that the measured backplane impedance is about 102 Ω. This very small tolerance of only 2 Ω results from strict conditions worked out using reliable and quality pc-board manufacturers. Measurements were performed using passive and active cards with real drivers that operate at 3.125 Gbits/s. The traces on the cards are 5 mils wide and 115 mm long. Figure 4b shows the eye diagram for the longest trace on the backplane situated in the worst-case layer.
The eye opening is about 509 mV—a strong result considering that the driver used for measurement requires at least a 200-mV opening. In a live system, performance is expected to be even better because additional noise introduced by the measurement cables and SMA contacts would be eliminated. Using standard FR-4 material wasn’t a problem. Employing various transceivers and SerDes devices, simulation and performance measurements showed that speeds of over 5 Gbits/s were reliable using FR4.
A good ATCA backplane design will consider issues such as hub slot placement, trace lengths, and intelligent routing strategy to optimize layer count and reduce costs. Further, these backplanes should be designed with plugging considerations in mind whereby shelf managers, fan trays, and headers receive signals from other Intelligent Platform Management Interface (IPMI)-enabled devices, etc.
Shelf Management
Shelf management is a critical element in carrier-grade computing platforms. Lately, shelf managers developed for the PICMG 3.0 specification use the IPMI. To maximize efficiency, one can incorporate a shelf manager that individually controls the fans in the chassis. Figure 1 also shows the shelf managers incorporated in a 5U ATCA unit.
For redundancy, another important issue in carrier-class systems, the shelf manager can be designed as dual units in a hot-swap redundant mode. It would support redundant operation with an automatic switchover, where one shelf manager will be active, while the other is a backup unit.
Finally, an interface board can be used for direct shelf-manager plugging. The interface board can be located either inside or outside of the ATCA card cage, offering great flexibility in design.
Developing a chassis that meets specific customer needs can be challenging for any specification, let alone a new one like ATCA. However, by adopting a step-by-step design methodology and using a comprehensive specification such as PICMG 3.0 for ATCA, it can be a springboard for the successful development of a CGOS.