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Today's Table of Contents: 1. Viewpoint Exclusive -- High-Speed Digital Design Is So... Analog
2. Pre-Silicon Prototyping For SoCs Gets A Lift
3. Barcelona Design Reaches Milestone at 130-nm Node
4. Denali Software Joins RapidIO Trade Association
5. Cadence Gets Get2Chip
6. Happenings
- 9th IEEE/DATC Electronic Design Processes (EDP) Workshop
- 24th Zuken Users Group North America
- 1st Zuken Users Group Europe
- 40th Design Automation Conference
- DesignCon East 2003
- Military & Aerospace Programmable Logic Device (MAPLD) Conference
- EuroDesignCon 2003
************ 1. Viewpoint - Exclusive to EDA Alert ************
High-Speed Digital Design Is So... Analog
Brad Cole, Product Marketing Manager, Signal Integrity Tools Ansoft Corp., Pittsburgh, Pa.
Signals fast enough to be considered high speed feature characteristics that are anything but digital. They undershoot and overshoot, their edge times degrade the further they travel, and they couple to signals on neighboring lines.
Calling a signal digital, however, implies that it occupies discrete levels. Typically, they correspond to a logical level “0” or a logical level “1”; however, they also may be multi-level. This digital point of view has served the design world very well over many years, allowing the explosion of computing power, information storage, and communication capacity. Yet, it is an abstraction of reality that's distorted by the physical-layer characteristics as signals are pushed to high speed.
The fact is, real signals are not just found at discrete levels, but rather are continuous. As speed climbs, jitter, eye closure, ground bounce, and ringing problems also increase. Clearly, high-speed signals don't remain neatly in well-defined discrete states, but are corrupted by analog effects.
The term analog effects is a shorthand way of saying that the signals in a device differ too radically from the digital abstraction to ignore some very real and important behavior. Indeed, signals that become more complicated when the path delay time is greater than the signal's rise time are more analog than digital. In this regime, distributed and full-wave effects become significant, and reflections caused by impedance mismatches play havoc, giving rise to such phenomena as data-dependent jitter or inter-symbol interference.
Although high-level system design is best accomplished in the digital domain, to get the design to actually work in practice at the physical level, it is necessary to treat the signal as analog. Together with constraints imposed by manufacturing costs and power consumption, these considerations combine to make high-speed pc-board and package design an exceptionally challenging undertaking.
High-speed board or package designers must draw upon a wealth of experience to be successful. Information must come from traditional digital design and from techniques used in the analog realm. Many of these techniques are common with microwave design and require a greater understanding of materials and manufacturing technology. Application of this wealth of information must be choreographed, but the combination of digital and analog design can produce amazing results.
With attention to analog effects comes the ability to more accurately model interconnects, reduce the number of design iterations, lower product development cost, improve time-to-market, receive that big promotion, buy your spouse a new car, and vacation in the South of France. Those who accept the challenge to go beyond digital design into the analog domain will reap the rewards. Fortunately, the capabilities of software products for circuit-level and geometry-based electromagnetic simulation are advancing rapidly. The newest SI design tools make it easy to see analog design for what it is: super-charged digital design.
Contact Brad Cole directly at: mailto:bcole@ansoft.com
******* 2. News *******
Pre-Silicon Prototyping For SoCs Gets A Lift
By introducing Flexible Prototyping Modules with Xilinx XC2V8000 Virtex-II Platform FPGAs, Aptix Corp. has delivered a suitable vehicle for SoC pre-silicon prototyping. The XC2V8000 Virtex-II FPGA supports an ASIC gate-equivalent capacity of 550,000-plus gates and includes over 3 Mbits of RAM, as well as intellectual-property (IP) distribution-enabling encryption capabilities.
A Flexible Prototyping Module contains one or two Xilinx XC2V6000 or XC2V8000 Virtex-II FPGA ICs, and up to ten of the modules can be plugged directly into the Aptix System Explorer and/or Software Integration Station. This provides a maximum gate capacity of over 10 million ASIC gates when using the dual-density XC2V8000 configuration. The Flexible Prototyping Modules are also compatible with the Aptix's systems software.
Available now, Aptix Pre-Silicon Prototyping Systems with the Flexible Prototyping Module start at $60,000.
Aptix Corp. ==> http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK062f0Af
******* 3. News *******
Barcelona Design Reaches Milestone at 130-nm Node
Barcelona Design Inc. achieved a major milestone in expanding its synthesizable analog IP offering. The company successfully completed comprehensive qualification, including silicon testing, of PLLs generated by its Miro Class 130-nm PLL engine. The PLLs are targeted at Taiwan Semiconductor Manufacturing Company's (TSMC) 130-nm process. In a related announcement, Barcelona stated that it also extended the Miro PLL class to support the TSMC NexSys 90-nm process technology. In September 2002, the company unveiled its plan to develop products at the 90-nm technology node. Barcelona expects to release the production 90-nm Miro PLL engine to customers in mid-2003. Barcelona Design ==> http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08Iw0AN
******* 4. News *******
Denali Software Joins RapidIO Trade Association
The RapidIO Trade Association and Denali Software Inc. report that Denali has become a member of the RapidIO Trade Association and is taking an active role in the definition of the flow control specification. An internationally certified, open standard that’s available today, RapidIO is the embedded interconnect performance leader for next-generation communications and networking systems applications. According to David Lin, Denali's vice president of business development, "We’re seeing great interest in RapidIO from our customers who depend on Denali software as they develop and verify advanced embedded-systems designs. We look forward to leveraging our infrastructure and enabling RapidIO-based systems for our customers in the near future." The RapidIO parallel and serial interconnect architectures are open standards available for review and download from the RapidIO Trade Association’s Web site. The Web site also provides information on system-enablement tools, including RapidIO vendor product lists, synthesizable Verilog cores, analog physical-layer cores, logic and protocol analyzers, operating-system support, bus functional models, and hardware interoperability platforms.
Denali ==> http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sN0AO RapidIO Trade Association==> http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sO0AP
******* 5. News *******
Cadence Gets Get2Chip
Cadence Design Systems Inc. has signed a definitive agreement to acquire Get2Chip, provider of advanced nanometer-scale synthesis technology to top chip and system design companies. Cadence plans to integrate Get2Chip's technology into its Cadence Encounter platform for digital integrated-circuit (IC) design.
Get2Chip's patented core technology, called "global focused synthesis," provides the industry's highest synthesis capacity and performance, and produces superior logic and interconnect structures for nanometer-scale physical design. Get2Chip's globally focused synthesis produces superior input to nanometer-scale placement and routing, resulting in rapid timing closure and higher-performance designs. It also provides improvements of up to 5X in run time and 10X in capacity relative to older synthesis architectures. Get2Chip's high capacity also enhances designer productivity by dramatically simplifying constraint definition and scripting.
Cadence plans to retain most of Get2Chip's employees and will continue to support all of Get2Chip's customers and products.
Cadence ==> http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK0paF0As
************* 6. Happenings *************
9th IEEE/DATC Electronic Design Processes (EDP) Workshop Monterey Beach Hotel, Monterey, Calif. April 21-23, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sP0AQ
24th Zuken Users Group North America Phoenix, Ariz. April 27-29, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sQ0AR
1st Zuken Users Group Europe Veldhoven, The Netherlands May 19-20, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sR0AS
40th Design Automation Conference Anaheim Convention Center, Anaheim, Calif. June 2-6, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sS0AT
DesignCon East 2003 Royal Plaza Hotel and Trade Center, Marlborough, Mass. June 23-25, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sT0AU
Military & Aerospace Programmable Logic Device (MAPLD) Conference Ronald Reagan Building and International Trade Center, Washington, D.C. September 9-11, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sU0AV
EuroDesignCon 2003 Arabella Sheraton Grand Hotel, Munich, Germany October 27-30, 2003 http://lists.planetee.com/cgi-bin3/DM/y/eQYi0DJhTw0BSK08sV0AW
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