EDA Alert: June 2, 2003

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com *ALL NEW*
June 2, 2003

=======================================

************************ ADVERTISEMENT **************************
SPONSORED BY: TRUE CIRCUITS, INC.
We offer a complete family of innovative, standardized and silicon proven
PLL designs that now feature LockNow! (TM) Technology for very fast locking
with minimal frequency overshoot. All PLLs are available in a range of
frequencies, multiplication factors and functions in TSMC and UMC processes
from 0.25 um to 0.09 um.
Call (650) 691-2500 or visit
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BACD0Ai
*****************************************************************

NEWS FLASH: At our newly redesigned Web site, http://www.elecdesign.com,
the power of Electronic Design is a mouse click away! Read our Web
exclusives, discover Featured Vendors, access our archives, share
viewpoints in our Forums, explore our e-newsletters, and more.

While at DAC this week, stop by one of the DACNet kiosks, visit the site,
and be sure to participate in our current Quick Poll: How will you
implement your next chip design?

Today's Table of Contents:
1. Viewpoint Exclusive -- Giving Designers The Power In Power Management
2. OpenAccess Coalition Debuts User-Driven Interoperability Roadmap
3. Monterey Muscles Into IBM's Blue Logic Methodology
4. Agilent Broadens Alliance With Cadence
5. Physical Design Exploration Accounts For Rectilinear Blocks
6. ADA, Partners Spin Automated Front-to-Back Analog/Mixed-Signal Flow
7. Happenings
- 40th Design Automation Conference
- DesignCon East 2003
- 9th Advanced Reticle Symposium
- 2003 HFSS Users Group Meeting
- Military & Aerospace Programmable Logic Device (MAPLD) Conference
- 6th Sophia Antipolis Forum On Microelectronics (SAME 2003)
- EuroDesignCon 2003
- International Workshop On IP-Based SoC Design

************
1. Viewpoint -- Exclusive to EDA Alert
************
Giving Designers The Power In Power Management
Ian Getreu, General Chair, 40th Design Automation Conference

Power management is becoming a major problem across the design spectrum due
to the shrinking of device technology and the associated increase in IC
functionality. Whether a designer creates handheld devices and looks to
extend battery life, or focuses on desktop systems built around advanced
processors, limiting power consumption is a pressing necessity.

The mounting pressures in power management can mostly be attributed to
higher performance, leading to greater device activity. Another major
contributor is shrinking device geometries that are driving up both active
and static leakage currents. Although dynamic power dissipation has
traditionally dominated power consumption, leakage current is demanding a
greater portion of the overall power budget as device geometries scale down
into the nanometer region. Fortunately, a whole slew of new approaches can
deal with these power challenges. These developments are occurring at the
device, circuit, and architectural levels. For example, methods such as
optimizing supply voltage and transistor threshold voltage can help make
the CMOS devices themselves more power efficient. At the same time, new
techniques that include clock gating and back biasing to dynamically change
threshold voltage, can be used to dynamically turn off sections of
circuitry that aren't being used at the time. At the highest level of
design abstraction, system designers can build in the structures that
enable the operating system to manage these dynamic power-management
structures to optimize the power expenditure with respect to desired system
performance. Relying on a combination of these device-level and
architectural run-time techniques will enable system designers to get a
much firmer grasp on power management, especially in battery-powered
devices.

Intelligent design tools are needed to help designers more effectively
examine power and performance tradeoffs. Then they can quickly and
accurately determine the optimal approach for their particular system.
Recognizing the growing importance of this topic, this week's 40th Design
Automation Conference has seven sessions devoted toward exploring the many
different aspects of design for power management--from managing leakage
power and power-grid analysis to energy-aware system design and low-power
embedded-system design. The full-day tutorial titled “Design Techniques for
Power Reduction” is of special interest, as it covers the entire gamut of
power-management techniques as well as the capabilities and limitations of
existing tools for power analysis and optimization.

Throughout the last 40 years of electronic development, one amazing fact
has emerged: No matter how daunting the task may be, once designers and EDA
developers focus their attention on a problem, they solve it! We may not be
able to anticipate how, but they do it. Thus we can be sure that the latest
challenge, power management, will be solved.

Contact Ian Getreu directly at: mailto:getreu@aol.com


************************ ADVERTISEMENT **************************
Cadence Design Systems

CADENCE ENABLES OPEN INTEROPERABILITY FOR NEXT-GENERATION IEEE VERILOG.
Broad technical donation, reference implementation, and IEEE 1364-2001
support to boost verification speed and efficiency. Find out more:
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcB0AE
or visit the Cadence theater (Booth 1311) - Thursday, June 4, 2003, 2:00PM
PST at DAC 2003.
*****************************************************************

*******
2. News
*******
OpenAccess Coalition Debuts User-Driven Interoperability Roadmap

The OpenAccess Coalition released its first user-driven roadmap for EDA
tool interoperability through 2005. The input and direction, via full
participation of the OpenAccess Coalition members, determined the changes
that the standard API and reference database will take over the next two
years.

The roadmap contains details on:

Near-term (2003) enhancements: Timing and electrical constraint support,
standardized process modeling for RLC extraction, X-router support,
enhanced technology data support (e.g., for OPC/PSM and package-level
analysis), support for functional models, and additional translators for
industry-standard formats.

Mid-term (mid-2004) enhancements: Improvements to handle design to
manufacturing, library modeling, system-in-package, library and design data
management, logical-to-physical hierarchy management extensions, improved
tool interoperability, additional extension language bindings (e.g., Perl),
IP security, reuse of extension data across applications, and manufacturing
test (ATPG).

Longer-term (2005 and beyond) enhancements: Formal, transistor-level
modeling support, and support for behavioral and architectural-level
constructs.

OpenAccess Coalition ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcC0AF

*******
3. News
*******
Monterey Muscles Into IBM's Blue Logic Methodology

Monterey Design Systems' design planner, which incorporates Monterey's
Progressive Refinement technology, has been qualified for inclusion in
IBM's Blue Logic standard ASIC design methodology. As part of the IBM Blue
Logic flow, the Monterey design planner starts the silicon virtual
prototyping process by automatically placing the large macros. The
resulting floorplan continues through the IBM Blue Logic methodology, until
the final physical implementation is complete. Qualification work for
Monterey's prototyper (Sonar) is also in process.

As part of the IBM Blue Logic methodology, the Monterey design planner will
be made available to all IBM Microelectronics ASIC design centers and its
customers.

Monterey Design ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcD0AG

*******
4. News
*******
Agilent Broadens Alliance With Cadence

In expanding its technology alliance with Cadence Design Systems, Agilent
Technologies Inc. intends to provide integrated design tools and
methodologies for fast, efficient wireless product development. Phase two
of the alliance builds on the Agilent RF Design Environment (RFDE) by
expanding current RF/mixed-signal IC circuit-level design capabilities to
add wireless system-level verification and layout analysis. This is
expected to help companies in the communications industry increase
productivity and speed development of wireless products, as well as further
reduce CAD infrastructure and total ownership costs. The jointly developed
products are expected to become available as early as the second half of
2003.

Agilent EEsof ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcE0AH

*******
5. News
*******
Physical Design Exploration Accounts For Rectilinear Blocks

Release 4.0 of Icinergy's front-end physical design exploration technology
introduces proven flows into Synopsys and Cadence physical synthesis and
gate-level virtual-prototyping tools. It also includes powerful new IP
library management capabilities.

Implementation of specific IP blocks often makes best sense as rectilinear
blocks, potentially because of port alignment issues, or to allow placement
of ports in specific locations. With the technology's new features,
designers can model rectilinear blocks right from the conceptual stage of
the design, increasing correlation between the early physical model and
implementation in back-end flows. Icinergy’s toolset permits rectilinear
blocks to contain hierarchy, so the early physical model contains all of
the information required by back-end tools.

Designers will also be able to create reusable, technology-independent port
definitions. Port definitions simplify the creation of standard interfaces,
and designers can quickly turn out bus structures by applying the
definitions to multiple blocks in a physical design.

Icinergy ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcF0AI

*******
6. News
*******
ADA, Partners Spin Automated Front-to-Back Analog/Mixed-Signal Flow

Analog Design Automation Inc. (ADA) has partnered with leading layout
vendors to integrate ADA’s front-end high-capacity optimization tools with
a range of layout solutions. The first announced partner vendors are
CiraNova, Sagantec, and Silicon Canvas.

This ADA initiative will address potential interoperability issues in both
the present and emerging analog design-tool markets. Analog and
mixed-signal designers are eager for increased vendor cooperation. Ensuring
that interoperability happens early, ADA believes, will make the design
process faster and easier and will accelerate the adoption of new analog
design tools.

Analog Design Automation ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcG0AJ

*************
7. Happenings
*************

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0paP0A6

DesignCon East 2003
Royal Plaza Hotel and Trade Center, Marlborough, Mass.
June 23-25, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK08el0Ah

9th Advanced Reticle Symposium
San Jose Convention Center, San Jose, Calif.
June 24, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcH0AK

2003 HFSS Users Group Meeting
Forum Hotel, Munich, Germany
July 9, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcI0AL

Military & Aerospace Programmable Logic Device (MAPLD) Conference
Ronald Reagan Building and International Trade Center, Washington, D.C.
September 9-11, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALX0AD

6th Sophia Antipolis Forum on Microelectronics (SAME 2003)
Sophia Antipolis, France
October 8-9, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcJ0AM

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALY0AE

International Workshop On IP-Based SoC Design
Espace Congres du World Trade Center, Grenoble, France
November 13-14, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALZ0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com

PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com *ALL NEW*
June 2, 2003

=======================================

************************ ADVERTISEMENT **************************
SPONSORED BY: TRUE CIRCUITS, INC.
We offer a complete family of innovative, standardized and silicon proven
PLL designs that now feature LockNow! (TM) Technology for very fast locking
with minimal frequency overshoot. All PLLs are available in a range of
frequencies, multiplication factors and functions in TSMC and UMC processes
from 0.25 um to 0.09 um.
Call (650) 691-2500 or visit
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BACD0Ai
*****************************************************************

NEWS FLASH: At our newly redesigned Web site, http://www.elecdesign.com,
the power of Electronic Design is a mouse click away! Read our Web
exclusives, discover Featured Vendors, access our archives, share
viewpoints in our Forums, explore our e-newsletters, and more.

While at DAC this week, stop by one of the DACNet kiosks, visit the site,
and be sure to participate in our current Quick Poll: How will you
implement your next chip design?

Today's Table of Contents:
1. Viewpoint Exclusive -- Giving Designers The Power In Power Management
2. OpenAccess Coalition Debuts User-Driven Interoperability Roadmap
3. Monterey Muscles Into IBM's Blue Logic Methodology
4. Agilent Broadens Alliance With Cadence
5. Physical Design Exploration Accounts For Rectilinear Blocks
6. ADA, Partners Spin Automated Front-to-Back Analog/Mixed-Signal Flow
7. Happenings
- 40th Design Automation Conference
- DesignCon East 2003
- 9th Advanced Reticle Symposium
- 2003 HFSS Users Group Meeting
- Military & Aerospace Programmable Logic Device (MAPLD) Conference
- 6th Sophia Antipolis Forum On Microelectronics (SAME 2003)
- EuroDesignCon 2003
- International Workshop On IP-Based SoC Design

************
1. Viewpoint -- Exclusive to EDA Alert
************
Giving Designers The Power In Power Management
Ian Getreu, General Chair, 40th Design Automation Conference

Power management is becoming a major problem across the design spectrum due
to the shrinking of device technology and the associated increase in IC
functionality. Whether a designer creates handheld devices and looks to
extend battery life, or focuses on desktop systems built around advanced
processors, limiting power consumption is a pressing necessity.

The mounting pressures in power management can mostly be attributed to
higher performance, leading to greater device activity. Another major
contributor is shrinking device geometries that are driving up both active
and static leakage currents. Although dynamic power dissipation has
traditionally dominated power consumption, leakage current is demanding a
greater portion of the overall power budget as device geometries scale down
into the nanometer region. Fortunately, a whole slew of new approaches can
deal with these power challenges. These developments are occurring at the
device, circuit, and architectural levels. For example, methods such as
optimizing supply voltage and transistor threshold voltage can help make
the CMOS devices themselves more power efficient. At the same time, new
techniques that include clock gating and back biasing to dynamically change
threshold voltage, can be used to dynamically turn off sections of
circuitry that aren't being used at the time. At the highest level of
design abstraction, system designers can build in the structures that
enable the operating system to manage these dynamic power-management
structures to optimize the power expenditure with respect to desired system
performance. Relying on a combination of these device-level and
architectural run-time techniques will enable system designers to get a
much firmer grasp on power management, especially in battery-powered
devices.

Intelligent design tools are needed to help designers more effectively
examine power and performance tradeoffs. Then they can quickly and
accurately determine the optimal approach for their particular system.
Recognizing the growing importance of this topic, this week's 40th Design
Automation Conference has seven sessions devoted toward exploring the many
different aspects of design for power management--from managing leakage
power and power-grid analysis to energy-aware system design and low-power
embedded-system design. The full-day tutorial titled “Design Techniques for
Power Reduction” is of special interest, as it covers the entire gamut of
power-management techniques as well as the capabilities and limitations of
existing tools for power analysis and optimization.

Throughout the last 40 years of electronic development, one amazing fact
has emerged: No matter how daunting the task may be, once designers and EDA
developers focus their attention on a problem, they solve it! We may not be
able to anticipate how, but they do it. Thus we can be sure that the latest
challenge, power management, will be solved.

Contact Ian Getreu directly at: mailto:getreu@aol.com


************************ ADVERTISEMENT **************************
Cadence Design Systems

CADENCE ENABLES OPEN INTEROPERABILITY FOR NEXT-GENERATION IEEE VERILOG.
Broad technical donation, reference implementation, and IEEE 1364-2001
support to boost verification speed and efficiency. Find out more:
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcB0AE
or visit the Cadence theater (Booth 1311) - Thursday, June 4, 2003, 2:00PM
PST at DAC 2003.
*****************************************************************

*******
2. News
*******
OpenAccess Coalition Debuts User-Driven Interoperability Roadmap

The OpenAccess Coalition released its first user-driven roadmap for EDA
tool interoperability through 2005. The input and direction, via full
participation of the OpenAccess Coalition members, determined the changes
that the standard API and reference database will take over the next two
years.

The roadmap contains details on:

Near-term (2003) enhancements: Timing and electrical constraint support,
standardized process modeling for RLC extraction, X-router support,
enhanced technology data support (e.g., for OPC/PSM and package-level
analysis), support for functional models, and additional translators for
industry-standard formats.

Mid-term (mid-2004) enhancements: Improvements to handle design to
manufacturing, library modeling, system-in-package, library and design data
management, logical-to-physical hierarchy management extensions, improved
tool interoperability, additional extension language bindings (e.g., Perl),
IP security, reuse of extension data across applications, and manufacturing
test (ATPG).

Longer-term (2005 and beyond) enhancements: Formal, transistor-level
modeling support, and support for behavioral and architectural-level
constructs.

OpenAccess Coalition ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcC0AF

*******
3. News
*******
Monterey Muscles Into IBM's Blue Logic Methodology

Monterey Design Systems' design planner, which incorporates Monterey's
Progressive Refinement technology, has been qualified for inclusion in
IBM's Blue Logic standard ASIC design methodology. As part of the IBM Blue
Logic flow, the Monterey design planner starts the silicon virtual
prototyping process by automatically placing the large macros. The
resulting floorplan continues through the IBM Blue Logic methodology, until
the final physical implementation is complete. Qualification work for
Monterey's prototyper (Sonar) is also in process.

As part of the IBM Blue Logic methodology, the Monterey design planner will
be made available to all IBM Microelectronics ASIC design centers and its
customers.

Monterey Design ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcD0AG

*******
4. News
*******
Agilent Broadens Alliance With Cadence

In expanding its technology alliance with Cadence Design Systems, Agilent
Technologies Inc. intends to provide integrated design tools and
methodologies for fast, efficient wireless product development. Phase two
of the alliance builds on the Agilent RF Design Environment (RFDE) by
expanding current RF/mixed-signal IC circuit-level design capabilities to
add wireless system-level verification and layout analysis. This is
expected to help companies in the communications industry increase
productivity and speed development of wireless products, as well as further
reduce CAD infrastructure and total ownership costs. The jointly developed
products are expected to become available as early as the second half of
2003.

Agilent EEsof ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcE0AH

*******
5. News
*******
Physical Design Exploration Accounts For Rectilinear Blocks

Release 4.0 of Icinergy's front-end physical design exploration technology
introduces proven flows into Synopsys and Cadence physical synthesis and
gate-level virtual-prototyping tools. It also includes powerful new IP
library management capabilities.

Implementation of specific IP blocks often makes best sense as rectilinear
blocks, potentially because of port alignment issues, or to allow placement
of ports in specific locations. With the technology's new features,
designers can model rectilinear blocks right from the conceptual stage of
the design, increasing correlation between the early physical model and
implementation in back-end flows. Icinergy’s toolset permits rectilinear
blocks to contain hierarchy, so the early physical model contains all of
the information required by back-end tools.

Designers will also be able to create reusable, technology-independent port
definitions. Port definitions simplify the creation of standard interfaces,
and designers can quickly turn out bus structures by applying the
definitions to multiple blocks in a physical design.

Icinergy ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcF0AI

*******
6. News
*******
ADA, Partners Spin Automated Front-to-Back Analog/Mixed-Signal Flow

Analog Design Automation Inc. (ADA) has partnered with leading layout
vendors to integrate ADA’s front-end high-capacity optimization tools with
a range of layout solutions. The first announced partner vendors are
CiraNova, Sagantec, and Silicon Canvas.

This ADA initiative will address potential interoperability issues in both
the present and emerging analog design-tool markets. Analog and
mixed-signal designers are eager for increased vendor cooperation. Ensuring
that interoperability happens early, ADA believes, will make the design
process faster and easier and will accelerate the adoption of new analog
design tools.

Analog Design Automation ==> http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcG0AJ

*************
7. Happenings
*************

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0paP0A6

DesignCon East 2003
Royal Plaza Hotel and Trade Center, Marlborough, Mass.
June 23-25, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK08el0Ah

9th Advanced Reticle Symposium
San Jose Convention Center, San Jose, Calif.
June 24, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcH0AK

2003 HFSS Users Group Meeting
Forum Hotel, Munich, Germany
July 9, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcI0AL

Military & Aerospace Programmable Logic Device (MAPLD) Conference
Ronald Reagan Building and International Trade Center, Washington, D.C.
September 9-11, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALX0AD

6th Sophia Antipolis Forum on Microelectronics (SAME 2003)
Sophia Antipolis, France
October 8-9, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BAcJ0AM

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALY0AE

International Workshop On IP-Based SoC Design
Espace Congres du World Trade Center, Grenoble, France
November 13-14, 2003
http://lists.planetee.com/cgi-bin3/DM/y/eRBF0DJhTw0BSK0BALZ0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com

PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.