EDA Alert: March 17, 2003

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
March 17, 2003

=======================================

************************ ADVERTISEMENT **************************
FREE FPGA Events from Mentor Graphics
Topics include:
~ High Performance Simulation
~ Achieving Timing closure using Physical Synthesis in today's advanced FPGAs
~ Empower your designs to meet the silicon of your choice
~ Designing with FPGA Advantage
~ VHDL & Verilog Verification and Test Bench Creation
Sign up today:
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08JK0Aq
*****************************************************************

Today's Table of Contents:
1. Viewpoint Exclusive -- SystemC, Anyone?
2. Cadence Sets Sights On Fast Serial Links For PCBs
3. Power/Signal-Integrity Tool Automates PCB And Package Analysis
4. Analog Synthesis Platform Enables Design Tradeoffs
5. Multicore Simulation Aids ARM Software Developers
6. STMicro Taps Agilent For RF/Mixed-Signal IC Design Flow
7. Happenings
- 13th Synopsys Users Group (SNUG) San Jose Conference
- 4th International Symposium on Quality Electronic Design
- System Level Interconnect Prediction (SLIP) 2003
- 9th IEEE/DATC Electronic Design Processes (EDP) Workshop
- 40th Design Automation Conference
- EuroDesignCon 2003

************
1. Viewpoint - Exclusive to EDA Alert
************
SystemC, Anyone?

Joan Bartlett, President, Actis Design, Portland, Ore.

The class library extension to C++, known as SystemC, is emerging as a viable
solution to the various design dilemmas created by the move to system-on-a-chip
(SoC) implementations. It has proven itself technically able to meet the needs
of next-generation designs and beyond, as massive amounts of detail demand a
higher level of design abstraction.

SystemC, a language built on an object-oriented foundation, provides fast
simulation performance. Based on C++, it can easily be used for hardware/software
integration and verification. It also allows designers to use familiar hardware
ideas such as modules and interfaces to model their design at high and
intermediate levels of abstraction. With such a combination of features,
designers can create software-development platforms much sooner in the design
process. This enables software integration and testing at the earliest possible
point. Results show greater parallel development cycles, which means earlier
time-to-market and increased quality of the final product.

C++ is the dominant language for system and software development. The addition
of SystemC class libraries with hardware-design-specific modeling constructs
increases the power of the language to meet the needs of next-generation
hardware design.

Today, designers use SystemC down to register-transfer-level (RTL) synthesis,
then an existing hardware description language (HDL) to complete the design
implementation. Soon, a “one-language” flow will be possible, using SystemC
from start to finish.

Whatever the implementation, hardware designers and software developers are
swiftly moving to SystemC. They also are completing more-complex systems at
a higher level of abstraction with greater satisfaction and higher degrees
of success. The SystemC language is free and can be downloaded at:
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08It0AW
Don’t you think it's time you checked out SystemC?

Contact Joan Bartlett directly at: mailto:joan@actisdesign.com

************************ ADVERTISEMENT **************************
Cadence Technical Seminar

Accelerate Your Time to Working Silicon in the Nanometer Era

At this informational one-day seminar, you'll discover the techniques and
technologies that can help you accelerate your time to working silicon.
Register now for Costa Mesa, Santa Clara, Austin, and Kanata, Ontario locations.

http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08JL0Ar
*****************************************************************

*******
2. News
*******
Cadence Sets Sights On Fast Serial Links For PCBs

Cadence Design Systems recently debuted a new methodology and solution for
designing and implementing multigigabit serial interfaces in high-speed pc
boards. The differential signal capability is part of the new 15.0 release
of the Cadence PCB Expert series design environment. The release includes
enhancements in SPECCTRAQuest SI Expert, Allegro layout, and SPECCTRA autorouter.

Users can now define a comprehensive set of rules within Allegro's Constraint Manager,
which enables constraint-driven layout in Allegro for differential signals. In
addition, Allegro can treat differential signal pairs as a single entity.

SPECCTRAQuest and Allegro now make it possible to edit an existing differential
signal, or group of differential signals, using interactive push/shove routing
while maintaining full electrical rule/constraint compliance. This feature
reduces the need for tedious post-edit re-simulation iterations.

Release 15.0 of the Cadence PCB Expert design environment will be available
in the Q2 2003 for the Solaris, HP-UX, IBM-AIX platforms, and Windows NT and
2000. The PCB Design Expert for high-speed design starts at a U.S. list price
of $25,200 for a one-year license, and includes Concept HDL Expert or Capture
CIS schematic, constraint and topology management, library management, Allegro
Expert for interactive PCB layout, and SPECCTRA Expert autorouter. SPECCTRAQuest
SI Expert starts at a U.S. list price of $25,200 for a one-year license.

Cadence ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0paF0A5

*******
3. News
*******
Power/Signal-Integrity Tool Automates PCB And Package Analysis

The latest version of Ansoft's power- and signal-integrity analysis tool,
SIwave v1.1, meets the growing demand for fast, accurate analysis of high-end
IC packages and pc boards. Using a hybrid, finite-element technique, SIwave
allows design engineers to characterize simultaneous switching noise, power
and ground bounce, resonances, reflections and coupling between traces, and
power/ground planes. Engineers also employ the software to simulate high-speed
devices with their own driver/receiver models. The models would use SIwave's
SPICE output to obtain accurate system-level simulations.

SIwave analyzes complex pc boards and IC packages consisting of multiple,
arbitrarily shaped power and ground layers and any number of vias, signal
traces, and lumped components. With SIwave, designers can model many types
of effects, including voltage; potential variation across complete power and
ground structures with or without decoupling capacitors; power and ground
bounce; simultaneous switching noise; and frequency-domain phenomena (such as
resonant modes and S parameters).

Circuit models providing all of these effects can be generated for use in HSpice
from Synopsys, PSpice from Cadence, or Ansoft's Maxwell Spice.

SIwave v1.1 is available immediately. It is supported on Windows 2000/XP, HP UX,
and Sun Solaris. U.S. Pricing starts at $49,900.

Ansoft ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iv0AY

*******
4. News
*******
Analog Synthesis Platform Enables Design Tradeoffs

Sophisticated tradeoff-analysis capabilities are incorporated into version 1.2
of Barcelona Design's Prado analog synthesis platform. The platform works with
Barcelona's portfolio of IP engines to synthesize customized, tapeout-ready IP
instances.

The tool's tradeoff analysis functions allow users to quickly evaluate performance
tradeoffs between different automatically synthesized circuits to determine how to
best satisfy system-level requirements. For example, used together with the Miró
class of clocking engines, the user can evaluate the correlation between power,
area, and various jitter performance measures for a given frequency specification
at the click of a button. Tradeoff analysis automatically generates the different
feasible circuit candidates, and the user can subsequently choose the circuit that
best satisfies a specific application requirement.

In addition to enabling tradeoffs within the phase-locked-loop (PLL) core itself,
the Prado platform makes it possible to optimize requirements at the system level.
For example, by analyzing changes in a PLL's reference frequency (i.e., the external
crystal oscillator specification) versus PLL area/cost and jitter performance, a
system designer can determine optimal PLL specifications in order to optimize SoC
performance/cost tradeoffs.

The Prado analog synthesis platform costs $100,000. It also requires an engine and
instance license, and those prices vary depending on type and quantity.

Barcelona Design ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iw0AZ

*******
5. News
*******
Multicore Simulation Aids ARM Software Developers

By integrating its ARM RealView debugger with its MaxSim Developer Suite, AXYS
Design Automation Inc. has fashioned a system enabling "operating-system-aware"
multicore debugging for mixed-architecture designs using combinations of ARM
processors and DSPs. The MaxSim Developer Suite combines the performance of
cycle-based C++ simulation at the transaction level with the flexibility of SystemC.
It unlocks the potential of SystemC by integrating it in a single, unified simulation
engine with more than 20 processor models, debuggers, and platform components.

Using the MaxLib model library, designers can develop and verify SystemC-based SoC
designs with microcontroller and DSP families from ARM, Adelante, Improv Systems,
Infineon, LSI Logic, and ParthusCeva. MaxSim implements a single kernel for multicore
debugging and provides operating-system awareness for Symbian, ThreadX, and Nucleus.
Support for additional DSPs and operating systems is planned.

The release 3.1 of MaxSim Developer Suite and the accompanying platform tools are
available now. Pricing starts at $12,000 per year.

AXYS Design ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0q4H0AO

*******
6. News
*******
STMicro Taps Agilent For RF/Mixed-Signal IC Design Flow

STMicroelectronics turned to Agilent's radio frequency design environment (RFDE) as
its environment of choice for RF/mixed-signal IC design. STMicroelectronics has
begun a phased approach to upgrading its R&D operations to the Agilent and Cadence
RFDE-based design flow.

Agilent RFDE is an RF design platform that tightly integrates RF simulation
technologies from Agilent's Advanced Design System (ADS) into Cadence Design
System's analog and mixed-signal design flow. RFDE is the first product to
result from the alliance with Cadence, giving analog and RF engineers access
to frequency-domain simulation technology from within the Cadence environment.

"Early guidance from ST really made a difference in this joint project with
Agilent," says Yaakov Milstain, corporate vice president and general manager
of Cadence's Custom IC Division. "Our customers are already seeing results
from the RF/mixed-signal IC alliance that we formed with Agilent, and they
can expect more to come. Our respective development teams are already collaborating
on the next phase of the alliance roadmap."

Agilent==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0IjM0Ah
STMicroelectronics ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0qFU0At

*************
7. Happenings
*************

13th Synopsys Users Group (SNUG) San Jose Conference
Doubletree Hotel, San Jose, Calif.
March 17-19, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Ix0Aa

4th International Symposium on Quality Electronic Design
Doubletree Hotel, San Jose, Calif.
March 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iy0Ab

System Level Interconnect Prediction (SLIP) 2003
Doubletree Hotel, Monterey, Calif.
April 5-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iz0Ac

9th IEEE/DATC Electronic Design Processes (EDP) Workshop
Monterey Beach Hotel, Monterey, Calif.
April 21-23, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I10AP

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I20AQ

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I30AR

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
March 17, 2003

=======================================

************************ ADVERTISEMENT **************************
FREE FPGA Events from Mentor Graphics
Topics include:
~ High Performance Simulation
~ Achieving Timing closure using Physical Synthesis in today's advanced FPGAs
~ Empower your designs to meet the silicon of your choice
~ Designing with FPGA Advantage
~ VHDL & Verilog Verification and Test Bench Creation
Sign up today:
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08JK0Aq
*****************************************************************

Today's Table of Contents:
1. Viewpoint Exclusive -- SystemC, Anyone?
2. Cadence Sets Sights On Fast Serial Links For PCBs
3. Power/Signal-Integrity Tool Automates PCB And Package Analysis
4. Analog Synthesis Platform Enables Design Tradeoffs
5. Multicore Simulation Aids ARM Software Developers
6. STMicro Taps Agilent For RF/Mixed-Signal IC Design Flow
7. Happenings
- 13th Synopsys Users Group (SNUG) San Jose Conference
- 4th International Symposium on Quality Electronic Design
- System Level Interconnect Prediction (SLIP) 2003
- 9th IEEE/DATC Electronic Design Processes (EDP) Workshop
- 40th Design Automation Conference
- EuroDesignCon 2003

************
1. Viewpoint - Exclusive to EDA Alert
************
SystemC, Anyone?

Joan Bartlett, President, Actis Design, Portland, Ore.

The class library extension to C++, known as SystemC, is emerging as a viable
solution to the various design dilemmas created by the move to system-on-a-chip
(SoC) implementations. It has proven itself technically able to meet the needs
of next-generation designs and beyond, as massive amounts of detail demand a
higher level of design abstraction.

SystemC, a language built on an object-oriented foundation, provides fast
simulation performance. Based on C++, it can easily be used for hardware/software
integration and verification. It also allows designers to use familiar hardware
ideas such as modules and interfaces to model their design at high and
intermediate levels of abstraction. With such a combination of features,
designers can create software-development platforms much sooner in the design
process. This enables software integration and testing at the earliest possible
point. Results show greater parallel development cycles, which means earlier
time-to-market and increased quality of the final product.

C++ is the dominant language for system and software development. The addition
of SystemC class libraries with hardware-design-specific modeling constructs
increases the power of the language to meet the needs of next-generation
hardware design.

Today, designers use SystemC down to register-transfer-level (RTL) synthesis,
then an existing hardware description language (HDL) to complete the design
implementation. Soon, a “one-language” flow will be possible, using SystemC
from start to finish.

Whatever the implementation, hardware designers and software developers are
swiftly moving to SystemC. They also are completing more-complex systems at
a higher level of abstraction with greater satisfaction and higher degrees
of success. The SystemC language is free and can be downloaded at:
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08It0AW
Don’t you think it's time you checked out SystemC?

Contact Joan Bartlett directly at: mailto:joan@actisdesign.com

************************ ADVERTISEMENT **************************
Cadence Technical Seminar

Accelerate Your Time to Working Silicon in the Nanometer Era

At this informational one-day seminar, you'll discover the techniques and
technologies that can help you accelerate your time to working silicon.
Register now for Costa Mesa, Santa Clara, Austin, and Kanata, Ontario locations.

http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08JL0Ar
*****************************************************************

*******
2. News
*******
Cadence Sets Sights On Fast Serial Links For PCBs

Cadence Design Systems recently debuted a new methodology and solution for
designing and implementing multigigabit serial interfaces in high-speed pc
boards. The differential signal capability is part of the new 15.0 release
of the Cadence PCB Expert series design environment. The release includes
enhancements in SPECCTRAQuest SI Expert, Allegro layout, and SPECCTRA autorouter.

Users can now define a comprehensive set of rules within Allegro's Constraint Manager,
which enables constraint-driven layout in Allegro for differential signals. In
addition, Allegro can treat differential signal pairs as a single entity.

SPECCTRAQuest and Allegro now make it possible to edit an existing differential
signal, or group of differential signals, using interactive push/shove routing
while maintaining full electrical rule/constraint compliance. This feature
reduces the need for tedious post-edit re-simulation iterations.

Release 15.0 of the Cadence PCB Expert design environment will be available
in the Q2 2003 for the Solaris, HP-UX, IBM-AIX platforms, and Windows NT and
2000. The PCB Design Expert for high-speed design starts at a U.S. list price
of $25,200 for a one-year license, and includes Concept HDL Expert or Capture
CIS schematic, constraint and topology management, library management, Allegro
Expert for interactive PCB layout, and SPECCTRA Expert autorouter. SPECCTRAQuest
SI Expert starts at a U.S. list price of $25,200 for a one-year license.

Cadence ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0paF0A5

*******
3. News
*******
Power/Signal-Integrity Tool Automates PCB And Package Analysis

The latest version of Ansoft's power- and signal-integrity analysis tool,
SIwave v1.1, meets the growing demand for fast, accurate analysis of high-end
IC packages and pc boards. Using a hybrid, finite-element technique, SIwave
allows design engineers to characterize simultaneous switching noise, power
and ground bounce, resonances, reflections and coupling between traces, and
power/ground planes. Engineers also employ the software to simulate high-speed
devices with their own driver/receiver models. The models would use SIwave's
SPICE output to obtain accurate system-level simulations.

SIwave analyzes complex pc boards and IC packages consisting of multiple,
arbitrarily shaped power and ground layers and any number of vias, signal
traces, and lumped components. With SIwave, designers can model many types
of effects, including voltage; potential variation across complete power and
ground structures with or without decoupling capacitors; power and ground
bounce; simultaneous switching noise; and frequency-domain phenomena (such as
resonant modes and S parameters).

Circuit models providing all of these effects can be generated for use in HSpice
from Synopsys, PSpice from Cadence, or Ansoft's Maxwell Spice.

SIwave v1.1 is available immediately. It is supported on Windows 2000/XP, HP UX,
and Sun Solaris. U.S. Pricing starts at $49,900.

Ansoft ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iv0AY

*******
4. News
*******
Analog Synthesis Platform Enables Design Tradeoffs

Sophisticated tradeoff-analysis capabilities are incorporated into version 1.2
of Barcelona Design's Prado analog synthesis platform. The platform works with
Barcelona's portfolio of IP engines to synthesize customized, tapeout-ready IP
instances.

The tool's tradeoff analysis functions allow users to quickly evaluate performance
tradeoffs between different automatically synthesized circuits to determine how to
best satisfy system-level requirements. For example, used together with the Miró
class of clocking engines, the user can evaluate the correlation between power,
area, and various jitter performance measures for a given frequency specification
at the click of a button. Tradeoff analysis automatically generates the different
feasible circuit candidates, and the user can subsequently choose the circuit that
best satisfies a specific application requirement.

In addition to enabling tradeoffs within the phase-locked-loop (PLL) core itself,
the Prado platform makes it possible to optimize requirements at the system level.
For example, by analyzing changes in a PLL's reference frequency (i.e., the external
crystal oscillator specification) versus PLL area/cost and jitter performance, a
system designer can determine optimal PLL specifications in order to optimize SoC
performance/cost tradeoffs.

The Prado analog synthesis platform costs $100,000. It also requires an engine and
instance license, and those prices vary depending on type and quantity.

Barcelona Design ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iw0AZ

*******
5. News
*******
Multicore Simulation Aids ARM Software Developers

By integrating its ARM RealView debugger with its MaxSim Developer Suite, AXYS
Design Automation Inc. has fashioned a system enabling "operating-system-aware"
multicore debugging for mixed-architecture designs using combinations of ARM
processors and DSPs. The MaxSim Developer Suite combines the performance of
cycle-based C++ simulation at the transaction level with the flexibility of SystemC.
It unlocks the potential of SystemC by integrating it in a single, unified simulation
engine with more than 20 processor models, debuggers, and platform components.

Using the MaxLib model library, designers can develop and verify SystemC-based SoC
designs with microcontroller and DSP families from ARM, Adelante, Improv Systems,
Infineon, LSI Logic, and ParthusCeva. MaxSim implements a single kernel for multicore
debugging and provides operating-system awareness for Symbian, ThreadX, and Nucleus.
Support for additional DSPs and operating systems is planned.

The release 3.1 of MaxSim Developer Suite and the accompanying platform tools are
available now. Pricing starts at $12,000 per year.

AXYS Design ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0q4H0AO

*******
6. News
*******
STMicro Taps Agilent For RF/Mixed-Signal IC Design Flow

STMicroelectronics turned to Agilent's radio frequency design environment (RFDE) as
its environment of choice for RF/mixed-signal IC design. STMicroelectronics has
begun a phased approach to upgrading its R&D operations to the Agilent and Cadence
RFDE-based design flow.

Agilent RFDE is an RF design platform that tightly integrates RF simulation
technologies from Agilent's Advanced Design System (ADS) into Cadence Design
System's analog and mixed-signal design flow. RFDE is the first product to
result from the alliance with Cadence, giving analog and RF engineers access
to frequency-domain simulation technology from within the Cadence environment.

"Early guidance from ST really made a difference in this joint project with
Agilent," says Yaakov Milstain, corporate vice president and general manager
of Cadence's Custom IC Division. "Our customers are already seeing results
from the RF/mixed-signal IC alliance that we formed with Agilent, and they
can expect more to come. Our respective development teams are already collaborating
on the next phase of the alliance roadmap."

Agilent==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0IjM0Ah
STMicroelectronics ==> http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK0qFU0At

*************
7. Happenings
*************

13th Synopsys Users Group (SNUG) San Jose Conference
Doubletree Hotel, San Jose, Calif.
March 17-19, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Ix0Aa

4th International Symposium on Quality Electronic Design
Doubletree Hotel, San Jose, Calif.
March 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iy0Ab

System Level Interconnect Prediction (SLIP) 2003
Doubletree Hotel, Monterey, Calif.
April 5-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08Iz0Ac

9th IEEE/DATC Electronic Design Processes (EDP) Workshop
Monterey Beach Hotel, Monterey, Calif.
April 21-23, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I10AP

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I20AQ

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo/y/eP250DJhUf0BSK08I30AR

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.