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FPGA Clusters Combine with Mesh Architectures
Date Posted: November 14, 2006 12:00 AM
Cluster Applications:
The simplest application for FPGA processing would be a set of linear operations like FIR filters running in parallel. A FIR filter is simply a sum of products. The current output is the weighted sum of some number of past inputs. It would be implemented with a chain of multipliers and adders, along with some temporary storage for the previous inputs.
Data would come to the system over a high-speed channel (or several channels) and be distributed across perhaps several FPGA modules. Each FPGA would be divided up to handle as many channels as possible. This would allow a large number of operations to process in parallel, so the overall throughput of the system would be even higher than if one FPGA did all the work.
More challenging applications might involve correlation, digital downconversion, or demodulation cores. In cases where an entire signal processing chain doesn’t fit on one FGPA, it’s a simple matter to build a chain or pipeline comprising several chips in a string. Output data from one chip would be carried over a parallel link to a chip on the same board or over a high-speed serial link to a chip on another board in the chassis board. Cores that implement all these functions are available for purchase from the FPGA manufacturers as well as third parties.
More Complex Problems
Some more complex problems might involve two-dimensional FFTs, which involve one-dimensional FFTs on the rows and columns of the image, with a “corner turn” in between. A classic mesh architecture such as the VXS Processor Mesh fits this problem very well. A 2dFFT is the basis for a large number of useful operations, like image correlators, SAR processors, and target recognition algorithms. FPGA implementations of these functions would be very fast and probably use less power than a solution using general-purpose processors.
Another interesting utilization for a complex application would be a real-time adaptive beamformer. Beamforming involves calculating a set of weights from an input data set and then applying these weights, which define the gain and phase for each array element, to the input data. The weights are calculated using a process called QR decomposition. QR decomposition is a method for solving a set of simultaneous equations for the unknown weights, which then define the required beam pointing direction. The QR core is fairly resource intensive, so a complex system might require several FPGAs to implement it fully. Again, a network of FPGAs configured as a mesh fits this problem well.