For modern high-performance electronic systems, it's common practice to break the system down into pluggable, line-replaceable modules. This gives system designers flexibility to connect subsystems with a variety of functions. It additionally allows for easy repair and upgradability.
Backplanes often are used to electrically interconnect modules with each other
via a multilayer printed wiring board (PWB). The most frequent packaging implementation
of the backplane is where modules are plugged in from the one side and are oriented
parallel to each other (Fig. 1, left).
Other implementations use midplanes, which are similar to backplanes except the modules are inserted into both sides of the board rather than one side. For example, midplanes interconnect modules (such as switch cards, line cards, processor cards, or disk arrays) on the front side of the midplane to modules on the back side. A midplane architecture may offer designers more flexibility to optimize their designs for many variables, from minimizing trace length to user serviceability.
Specialized connectors, common to backplane and midplane implementations, are used to provide the blindmate separable interface. Connectors of this type must permit a routing channel in a direction normal to the card face to both escape the connector's footprint and allow for through routing channels.
As signal densities increase, routing these systems will boost the number of
signal layers and result in thicker, higher-cost circuit boards. Thicker boards
also adversely affect electrical performance by increasing the via stub, impedance,
and footprint crosstalk. Front and rear cards plug into the midplanes with various
orientations. One specific midplane implementation has front and rear cards
oriented orthogonally with respect to each other (Fig.
1, right).
Orthogonal system architectures can bring significant advantages for applications requiring the need for future speed upgrades using the same midplane. Because most of the trace, and its associated limitation in electrical performance, is moved from the midplane to the daughtercard, upgrades are simplified.
Greater interconnect performance is accomplished by just upgrading the modules.
In addition, because the midplane has minimal trace length, standard FR-4 boards
can be used instead of more exotic high-performance materials. All of these
factors will result in lower system cost. Another sometimes overlooked benefit
is that this midplane construction doesn't determine the physical-layer network
topology, enabling the system to be reconfigured to meet the customer's future
performance needs.
By minimizing traces routed through connector fields across the midplane, the overall skew and impedance control within the differential pair is more manageable. The resulting system is a well-controlled link in terms of impedance, skew, and attenuation management, with significant cost advantages over traditional backplane or midplane designs.
A few obstacles have prevented the potential mainstream adoption of orthogonal
midplane architectures, though—the thermal challenges in aircooled systems
and the nonlinear insertion loss seen with short traces and standard backplane
connectors. If it isn't addressed, the nonlinear insertion loss will diminish
the signal-integrity benefits. But with careful attention to choosing the correct
connector, the advantages of orthogonal architectures can be realized.
STANDARD BACKPLANE CONNECTORS
The electrical performance of a backplane interconnect is determined by linking
together all of the individual components in the channel. In an orthogonal architecture,
it's possible to improve the footprint and connector by using a differential
shared plated through-hole (DSPTH) configuration.
In addition, designers can improve transmission effects by removing the plated through-hole (PTH) stubs. Also, optimizing vias for the increased pitch between signal pairs dramatically lowers the crosstalk values in the footprints. Still, how the individual elements on the link interact isn't obvious.
In an orthogonal architecture using a traditional connector system, two connectors
are usually placed on opposite sides of the midplane with a small amount of
trace interconnecting them. Figure 2 illustrates
the routing for a typical midplane in an orthogonal system.
The PTH normally has a poor impedance match to the connectors and midplane traces. The close proximity of these two elements means the reflections (or return loss problems) will interact. The reflected energy from each impedance mismatch won't dissipate before reflecting off the next impedance mismatch. The routing diagram shows the proximity of the impedance mismatch on the midplane. The daughtercard footprints/traces, connectors, and midplane traces all have different impedance structures, resulting in a number of reflections.
Figure 3 shows a differential time-domain-reflectometer
(TDR) plot, with each element of the link labeled, and a frequency-domain measurement
plot of a traditional orthogonal interconnect without DSPTH technology. Each
of the link's elements are labeled. The PTH, or via, on the daughtercard and
the backplane each has approximately 50-mil stubs, and both use an 18-mil finished
hole diameter. The impedance of the two connectors is approximately 105 Ω
the daughtercard trace impedance is centered at 100 Ω and backplane-etch
is approximately 95 Ω Many available publications discuss the resonance
caused by a via stub. From this work and other simulations, it can be assumed
that the resonance of a 0.05-in. via stub will be above 10 GHz, most likely
in the region of 15 GHz. Yet when this link is analyzed with a vector network
analyzer (VNA), there's increased insertion loss at frequencies as low as 2
GHz. This is due to the accumulation of impedance discontinuities.
As the via stub grows (and the return loss increases), the interaction between the different impedance mismatches results in a nonlinear channel. The frequency-domain measurements of a similar channel are displayed, with the stub length increased to 0.120 in. and the backplane connectors interconnected with 2.5 in. of trace.
The dramatic change in the insertion loss between 1.8 and 2.4 GHz for the 2.5-in.
trace should be noted. In a span of less than 600 MHz, the insertion loss increases
by 4 dB. It's difficult to compensate for abrupt changes in the insertion loss
of the channel.
Channels with linear loss are easier to recover than nonlinear channels. Higher-order equalization (decision feedback and multitap feed forward) must be used to recover nonlinear channels.
As the complexity of silicon devices increases (to implement these equalization techniques), transceiver power consumption also elevates. Channel recovery in digital systems is never optimal due to the limited resolution of filter coefficients and the coarse time steps that they're spaced on.