Military and avionics applications must be rugged and offer high performance while meeting tight size, weight, and power (SWaP) requirements. High-performance computing (HPC) solutions in particular are in demand because achieving high performance while meeting those other requirements isn’t always easy (see “Military HPC Needs Software And Delivery Platforms,” p. xx).
The range of applications seems almost endless with ever larger computing projects on the drawing boards. Phased radar arrays can deliver finer images and track more targets with more computing power behind them. Unmanned aerial vehicles (UAVs) can perform more computing on board, reducing download bandwidth requirements.
Designers deliver this performance with a range of technologies, from high-speed serial interfaces to multicore CPUs, DSPs, and graphics processing units (GPUs) with a healthy sprinkling of FPGAs. Board form factors like VME, CompactPCI, VXS (VITA 41), and VPX (VITA 46) can support this range of processing chips. Conduction-cooled VPX boards running at 48 V can handle up to 768 W. This translates into lots of computing power. All but VME support high-speed serial interfaces.
The OpenVPX standard simplifies the fabric interconnect possibilities (see “OpenVPX Simplifies Rugged Design Tasks” at electronicdesign.com). This is key because high-speed serial fabrics are critical for HPC in these environments.
Big Jobs Need Fast Fabrics
The high-speed serial fabrics supported by OpenVPX include PCI Express (PCIe), Ethernet, Serial Rapid IO (SRIO), and InfiniBand. InfiniBand is popular for many HPC applications, but it’s even moreso in the scientific and enterprise arenas. PCIe tends to lack the peer-to-peer communications support that the other protocols have. PCIe also is used extensively for its designed purpose, interfacing processors to devices.
This leaves Ethernet and SRIO. Both are used extensively in military, avionics, and communications. Platforms like Curtiss-Wright Control Embedded Computing’s CHAMP-AV8 include both as well as PCIe to access peripherals (Fig. 1). On thing that’s different with this board is that it supports SRIO and Intel’s Core i7 processor.
The CHAMP-AV8 has two Core i7s, which is significant for two reasons (Fig. 2). First, SRIO isn’t a native interface for x86 processors. Ethernet and PCIe tend to be the interfaces found on the support chips. Native SRIO interfaces are found in many Power architecture processors. Second, Curtiss-Wright is using IDT’s PCIe 2 to SRIO 2 bridge chip, which simplifies the board designer’s job and provides a standard interface to the programmer.
The IDT chip is an SRIO adapter just like an Ethernet adapter. The primary difference between the two is the underlying protocol. SRIO tends to do better with smaller packet sizes because of its lower overhead (Fig. 3). It also provides guaranteed delivery. Ethernet targets larger packets and supports protocols like TCP/IP, which are needed to provide acknowledged delivery of data. Ethernet provides flexibility, but SRIO delivers better performance.
Bridging PCIe and SRIO is more than possible with IDT’s chip. FPGAs have been handling this chore for a while, and they were used initially when SRIO was being designed. The serializers-deserializers (SERDES) found on most of the high-performance FPGAs can handle any of the high-speed serial protocols like SRIO and Gigabit Ethernet.