Manage Network Traffic In Your 100-Gbit/s Designs

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Per Limbre

Network processor must handle range of applications

100G Ethernet requires a single scheduler

The queue manager writes packets to DRAM

Key Traffic Manager Features

Traffic-manager design was once a straightforward process for packet-switching systems operating at a few gigabits per second. Packet buffers could simply be implemented in high-volume, power-efficient, cost-effective DRAM. That’s now much more complicated.

Some of the basic design assumptions just don’t apply in today’s high-performance networking systems, where single processing devices control 100 Gbits/s of traffic. To better understand the current environment, this article explains the limitations and explores how packet buffers and traffic-management logic can be designed to meet the requirements for 100-Gbit/s designs and beyond.

TMs In Today’s Broadband Networks

Internet routers, access switches, and mobile gateways include deep packet buffers and logic to manage traffic in times of congestion. These systems, generally called TMs, play a critical role in modern broadband networks. They’re used mainly for two purposes: to enforce service-level agreements as contracted between service providers and their customers, and to maintain quality-of-service (QoS) attributes for traffic across network bottlenecks such as switching or compute resources.

Dedicated devices often implement TMs and associated packet buffers with fast silicon. Recent network processors (NPUs) integrate this logic to provide consistent packet processing and traffic management in a single device, reducing the bill of materials (BOM) and power consumption.

NPUs are quickly becoming popular in the latest carrier-networking products. Consequently, we can expect traffic-management capabilities, which were previously limited to high-end broadband edge routers, to become more generally available in cost-optimized networking nodes (e.g., Optical Line Terminal, Metro Ethernet aggregation, packet-optical transport systems).