Cascode Configuration Removes Miller Effect, Boosts PFC Performance

The power factor corrector (PFC) front end of an off-line power supply is subject to the operating frequency limitation caused by the Miller Effect of its associated power MOSFET. This effect is a property of any transistor configuration with a common source (MOSFET) or common emitter (bipolar transistor) configuration.

Most PFCs employ a boost converter based on a configuration with a common source MOSFET or common emitter power bipolar transistor. Figure 1 shows a conventional boost PFC kernel using a common source power MOSFET (Q). This is essentially a high gain amplifier that controls power by storing and releasing it into inductor L. During the MOSFET ON and OFF states, its drain voltage (V_DS) swings between almost zero and PFC output, which is generally 200V to 400V. This voltage periodically recharges the MOSFET's drain-to-source (C_DS) and drain-to-gate (C_DS) capacitances, and affects the gate-to-source (C_GS) capacitance (Fig. 2).

It's important to keep in mind that the V DS and drain-to-gate voltage (V_DG) are in counter-phase with respect to the V_GS and E_IN driving voltage. This means there is a negative feedback from the drain-to-gate, which is the Miller Effect¹ The Miller Effect increases the apparent input capacitance of a MOSFET or bipolar transistor.

To see the impact of the Miller Effect, consider how the boost transistor's input current depends on the Miller Effect and ignore the timing approach. The MOSFET's internal gate resistance (R_G) (Fig. 2, again) isn't essential and may be left out of the analysis.

Considering the MOSFET as an amplifier with negative feedback, notice that the following holds true if a small step input (E_IN) is applied to it:

dV_DG = dV_GS - dV_DS            (1)

where V_DG = drain-to-gate voltage; V_GS = gate-to-source voltage, and V_DS = drain-to-source voltage.

Here, we are dealing with very small values, so they will be described by their differentials, but:

dV_DS = - dI_D × Z_L            (2)

where dI_D = MOSFET drain current change and Z_L = load impedance .

Then:

dI_D = S × dV_GS            (3)

where S = slope of the MOSFET's transconductance.

Substituting dI_D from Eq. 3 into Eq. 2 will obtain:

dV_DS = -S × Z_L × dV_GS            (4)

Here, the expression for (S × Z_L) is the gain G of the amplifier built upon the MOSFET. The "minus" sign reflects the negative feedback. Thus,

G = S × Z_L            (5)

With the assumption of Eq. 5, Eq. 4 is:

dV_DS = -G × dV_GS           (6)

Substituting Eq. 6 into Eq. 1 for dV DS obtains:

dV_DG = dV_GS + G × dV_GS = dV_GS × (1 + G)           (7)

The input current (I_IN) splits into two components, as shown in Figure 2:

I_GD = Current flowing from MOSFET gate-to-drain

I_GS = Current flowing from MOSFET gate-to-source:

I_IN = I_GD + I_GS            (8)

The change of the gate-to-drain charge (Q_DG) causes current dI_GD so that:

I_GD = dQ_DG /dt           (9)

Therefore,

I_GD = dQ_DG/dt = C_DG × dV_DG/dt            (10)

or, assuming Eq. 7,

I_GD = dQ_DG/dt = C_DG × (1 + G) × dV_GS/dt            (11)

And,

I_GS = C_GS × dV_GS/dt            (12)

Consequently,

I_IN = C_DG × (1 + G) × dV_GS/dt + C _GS × dV_GS/dt

or

I_IN = [C_GS + C_DG × (1 + G) × dV_GS/dt            (13)

where C_GS + C_DG × (1 + G) = C_APP is the apparent input capacitance of the MOSFET, which has to be recharged by the input current I IN . The value of the apparent capacitance C_APP can be very high and subsequently, the input current should have extremely high values, too.

Therefore,

I_IN = C_APP × dV_GS/dt           (14)

For example, for the IXYS IXFR48N50Q MOSFET has the following characteristics along with circuit components:

C_GS = 7nF

C_DG = 0.230 nF

S = 30

Z_L = 230 Ω (PFC inductor inductance)

L = 300 µH ] @ 125 kHz operating frequency) and, therefore:

G = S × Z_L = 30 × 236 = 7000

And

C_APP = 0.230 × (1 + 7000) + 7 = 1.617 (µF)

The power factor corrector (PFC) front end of an off-line power supply is subject to the operating frequency limitation caused by the Miller Effect of its associated power MOSFET. This effect is a property of any transistor configuration with a common source (MOSFET) or common emitter (bipolar transistor) configuration.

Most PFCs employ a boost converter based on a configuration with a common source MOSFET or common emitter power bipolar transistor. Figure 1 shows a conventional boost PFC kernel using a common source power MOSFET (Q). This is essentially a high gain amplifier that controls power by storing and releasing it into inductor L. During the MOSFET ON and OFF states, its drain voltage (V_DS) swings between almost zero and PFC output, which is generally 200V to 400V. This voltage periodically recharges the MOSFET's drain-to-source (C_DS) and drain-to-gate (C_DS) capacitances, and affects the gate-to-source (C_GS) capacitance (Fig. 2).

It's important to keep in mind that the V DS and drain-to-gate voltage (V_DG) are in counter-phase with respect to the V_GS and E_IN driving voltage. This means there is a negative feedback from the drain-to-gate, which is the Miller Effect¹ The Miller Effect increases the apparent input capacitance of a MOSFET or bipolar transistor.

To see the impact of the Miller Effect, consider how the boost transistor's input current depends on the Miller Effect and ignore the timing approach. The MOSFET's internal gate resistance (R_G) (Fig. 2, again) isn't essential and may be left out of the analysis.

Considering the MOSFET as an amplifier with negative feedback, notice that the following holds true if a small step input (E_IN) is applied to it:

dV_DG = dV_GS - dV_DS            (1)

where V_DG = drain-to-gate voltage; V_GS = gate-to-source voltage, and V_DS = drain-to-source voltage.

Here, we are dealing with very small values, so they will be described by their differentials, but:

dV_DS = - dI_D × Z_L            (2)

where dI_D = MOSFET drain current change and Z_L = load impedance .

Then:

dI_D = S × dV_GS            (3)

where S = slope of the MOSFET's transconductance.

Substituting dI_D from Eq. 3 into Eq. 2 will obtain:

dV_DS = -S × Z_L × dV_GS            (4)

Here, the expression for (S × Z_L) is the gain G of the amplifier built upon the MOSFET. The "minus" sign reflects the negative feedback. Thus,

G = S × Z_L            (5)

With the assumption of Eq. 5, Eq. 4 is:

dV_DS = -G × dV_GS           (6)

Substituting Eq. 6 into Eq. 1 for dV DS obtains:

dV_DG = dV_GS + G × dV_GS = dV_GS × (1 + G)           (7)

The input current (I_IN) splits into two components, as shown in Figure 2:

I_GD = Current flowing from MOSFET gate-to-drain

I_GS = Current flowing from MOSFET gate-to-source:

I_IN = I_GD + I_GS            (8)

The change of the gate-to-drain charge (Q_DG) causes current dI_GD so that:

I_GD = dQ_DG /dt           (9)

Therefore,

I_GD = dQ_DG/dt = C_DG × dV_DG/dt            (10)

or, assuming Eq. 7,

I_GD = dQ_DG/dt = C_DG × (1 + G) × dV_GS/dt            (11)

And,

I_GS = C_GS × dV_GS/dt            (12)

Consequently,

I_IN = C_DG × (1 + G) × dV_GS/dt + C _GS × dV_GS/dt

or

I_IN = [C_GS + C_DG × (1 + G) × dV_GS/dt            (13)

where C_GS + C_DG × (1 + G) = C_APP is the apparent input capacitance of the MOSFET, which has to be recharged by the input current I IN . The value of the apparent capacitance C_APP can be very high and subsequently, the input current should have extremely high values, too.

Therefore,

I_IN = C_APP × dV_GS/dt           (14)

For example, for the IXYS IXFR48N50Q MOSFET has the following characteristics along with circuit components:

C_GS = 7nF

C_DG = 0.230 nF

S = 30

Z_L = 230 Ω (PFC inductor inductance)

L = 300 µH ] @ 125 kHz operating frequency) and, therefore:

G = S × Z_L = 30 × 236 = 7000

And

C_APP = 0.230 × (1 + 7000) + 7 = 1.617 (µF)