Cascode Configuration Removes Miller Effect, Boosts PFC Performance

It's clear that the input current must recharge this capacitance at the operating rate of, say, 15 V per 100 ns or 150 V /µs

And, from Equation 14, I_IN is 242.5 A.

Actually, C_DG and C_DS can vary by more than one order of magnitude or more when voltages V_GS and V_DS change (they reduce dramatically when these voltages rise from 0 to 40 V). The average I IN would not be that great, but instant values of about 10 to 20 A are possible. The MOSFET drivers can't produce this amount of current, which induces the well-known plateau on the MOSFET gate-drive characteristic (Fig. 3).²

So, the Miller Effect causes the apparent C_DG increase by a factor of a MOSFET amplifier gain, which can be on the order of a few thousand. This established negative feedback dramatically reduces the MOSFET's switching process, causing the above mentioned plateau in the gate-to-source signal timing diagram (Fig. 3, again). The Miller Effect limits the boost converter's (PFC) operating frequency to the values, which are far below the IC's and MOSFET's capabilities.

Zero voltage transition helps avoid the Miller Effect because the boost transistor drain-to-source voltage (V_DS) is controlled by an external resonant circuit ^3,4 , not the MOSFET's gate signal (E_IN). This very reliable method requires another high-voltage MOSFET, a resonant inductor, two high-voltage diodes, and a handful of snubbing components, which suppress parasitic oscillations caused by the extra rectification diode as well as the inductor and its stray parameters. Power supplies operating above 800 W employ this type of PFC. Figure 4 shows waveforms of the gate drive and drain voltage.

For smaller power rates, a cascode configuration may be welcome. It's proven to be an easy and inexpensive solution. Because it's free of the Miller Effect, it helps to substantially increase the PFC operating frequency.

A very good example of a cascode schematic arrangement is described in an article authored by Scot Lester.⁵ This paper discusses the input and output voltage increase in the cascode configuration. However, it leaves out a more important ability of a cascode scheme—getting rid of the Miller Effect to enable operation at higher frequencies.

Figure 5 depicts a cascode amplifier employing boost controller U1 (Texas Instruments' UC3854A may be a good implementation), driving a low-voltage and low- R_DS MOSFET (Q1) through resistor R. This common source configuration has a very-low-impedance drain load because high-voltage transistor Q2 is a common-gate configuration (Fig. 6), and Q1 "sees" its source. In operation, the Q1 drain voltage swing is only about V_CC, while the load is a very low impedance. This doesn't trigger the Miller Effect due to a very low voltage gain of Q1. The upper high-voltage MOSFET Q2 has a common gate connection, which eliminates the negative feedback and thus the Miller Effect. This is why the apparent capacitance of Q2 is just the gate-to-source capacitance (and even less due to the positive feedback through Q2, C_DS).

During operation, both Q1 and Q2 are either ON or OFF. When the Q2 drain voltage changes rapidly, it affects the gate and source networks through capacitances C_DG and C_DS. Diode D serves as a clamp for the Q2 source, connecting it to the V_CC when Q2 turns off and its drain pulls up the source through the C_DS. It's worth mentioning that the Q2 drain seriously affects the Q2 gate circuit, which tends to change the V_CC. To prevent this, the source of the V_CC should be able to resist both pull-up and pull-down changes, providing substantial sinking and sourcing currents. The V_CC source can be made upon a linear voltage regulator LM78L15 and an operational amplifier, capable of producing output current of around 1 A. ON Semiconductor's TCA0372 may be a good choice for this step.

Figures 7 and 8 show a cascode configuration. The waveforms have no evidence of the Miller Effect. The cascode solution can be used at frequencies far above those being operated at by conventional PFCs.

References

1. John M. Miller, "Dependence of the Input Impedance of a Three-Electrode Vacuum Tube upon the Load in the Plate Circuit," Scientific Papers of the Bureau of Standards, 15 (351): 367 - 385, 1920.
2. Jess Brown, "Developing Analytical Equations for Determining Power MOSFET Switching Transients," www.powermanagementdesignline.com, December 13, 2004
3. Christophe Basso, "Get Rid of the Miller Effect with Zero Voltage Switching," Power Electronics Technology , November 2004, pp 62 - 63 .
4. Jim Noon, "UC3855A/B High Performance Power Factor Pre-regulator," Texas Instruments Application Report SLUA146A Rev ., April 2004.
5. Scot Lester, "Cascode MOSFET Increases Boost Regulator's Input-and-Output Ranges," EDN , September 2005, pp 86, 88.

It's clear that the input current must recharge this capacitance at the operating rate of, say, 15 V per 100 ns or 150 V /µs

And, from Equation 14, I_IN is 242.5 A.

Actually, C_DG and C_DS can vary by more than one order of magnitude or more when voltages V_GS and V_DS change (they reduce dramatically when these voltages rise from 0 to 40 V). The average I IN would not be that great, but instant values of about 10 to 20 A are possible. The MOSFET drivers can't produce this amount of current, which induces the well-known plateau on the MOSFET gate-drive characteristic (Fig. 3).²

So, the Miller Effect causes the apparent C_DG increase by a factor of a MOSFET amplifier gain, which can be on the order of a few thousand. This established negative feedback dramatically reduces the MOSFET's switching process, causing the above mentioned plateau in the gate-to-source signal timing diagram (Fig. 3, again). The Miller Effect limits the boost converter's (PFC) operating frequency to the values, which are far below the IC's and MOSFET's capabilities.

Zero voltage transition helps avoid the Miller Effect because the boost transistor drain-to-source voltage (V_DS) is controlled by an external resonant circuit ^3,4 , not the MOSFET's gate signal (E_IN). This very reliable method requires another high-voltage MOSFET, a resonant inductor, two high-voltage diodes, and a handful of snubbing components, which suppress parasitic oscillations caused by the extra rectification diode as well as the inductor and its stray parameters. Power supplies operating above 800 W employ this type of PFC. Figure 4 shows waveforms of the gate drive and drain voltage.

For smaller power rates, a cascode configuration may be welcome. It's proven to be an easy and inexpensive solution. Because it's free of the Miller Effect, it helps to substantially increase the PFC operating frequency.

A very good example of a cascode schematic arrangement is described in an article authored by Scot Lester.⁵ This paper discusses the input and output voltage increase in the cascode configuration. However, it leaves out a more important ability of a cascode scheme—getting rid of the Miller Effect to enable operation at higher frequencies.

Figure 5 depicts a cascode amplifier employing boost controller U1 (Texas Instruments' UC3854A may be a good implementation), driving a low-voltage and low- R_DS MOSFET (Q1) through resistor R. This common source configuration has a very-low-impedance drain load because high-voltage transistor Q2 is a common-gate configuration (Fig. 6), and Q1 "sees" its source. In operation, the Q1 drain voltage swing is only about V_CC, while the load is a very low impedance. This doesn't trigger the Miller Effect due to a very low voltage gain of Q1. The upper high-voltage MOSFET Q2 has a common gate connection, which eliminates the negative feedback and thus the Miller Effect. This is why the apparent capacitance of Q2 is just the gate-to-source capacitance (and even less due to the positive feedback through Q2, C_DS).

During operation, both Q1 and Q2 are either ON or OFF. When the Q2 drain voltage changes rapidly, it affects the gate and source networks through capacitances C_DG and C_DS. Diode D serves as a clamp for the Q2 source, connecting it to the V_CC when Q2 turns off and its drain pulls up the source through the C_DS. It's worth mentioning that the Q2 drain seriously affects the Q2 gate circuit, which tends to change the V_CC. To prevent this, the source of the V_CC should be able to resist both pull-up and pull-down changes, providing substantial sinking and sourcing currents. The V_CC source can be made upon a linear voltage regulator LM78L15 and an operational amplifier, capable of producing output current of around 1 A. ON Semiconductor's TCA0372 may be a good choice for this step.

Figures 7 and 8 show a cascode configuration. The waveforms have no evidence of the Miller Effect. The cascode solution can be used at frequencies far above those being operated at by conventional PFCs.

References

1. John M. Miller, "Dependence of the Input Impedance of a Three-Electrode Vacuum Tube upon the Load in the Plate Circuit," Scientific Papers of the Bureau of Standards, 15 (351): 367 - 385, 1920.
2. Jess Brown, "Developing Analytical Equations for Determining Power MOSFET Switching Transients," www.powermanagementdesignline.com, December 13, 2004
3. Christophe Basso, "Get Rid of the Miller Effect with Zero Voltage Switching," Power Electronics Technology , November 2004, pp 62 - 63 .
4. Jim Noon, "UC3855A/B High Performance Power Factor Pre-regulator," Texas Instruments Application Report SLUA146A Rev ., April 2004.
5. Scot Lester, "Cascode MOSFET Increases Boost Regulator's Input-and-Output Ranges," EDN , September 2005, pp 86, 88.