BGA-style dc-dc building blocks implement a new distributed power architecture that promises higher performance and lower cost. Bricks and SIPs, more generically known as dc-dc converters, have long been the basic building blocks of distributed power architectures. Over time, the performance of these modules has been improved to meet a variety of system demands for higher efficiencies and current densities, smaller packages, and lower cost. At the same time, architectural refinements, like the intermediate voltage bus, have helped designers deal with the increasing number of supply voltages, faster load transients, and falling supply voltages.
But as system requirements continue to become more challenging, conventional distributed power architectures and existing dc-dc converters may have great difficulty keeping up with system demands. Vicor has responded by redrawing the distributed power scheme into what it calls the Factorized Power Architecture (FPA). This new approach to distributed power takes the basic power-conversion functions—isolation, voltage conversion, regulation, and EMI suppression—and re-orders them within novel IC-style devices. The effect is significantly improved electrical performance, greater reliability, and lower cost. These benefits accrue from the performance of the power devices employed as well as from the inherent flexibility of the new architecture.
The company implemented FPA as a family of BGA-style devices called V•I Chips. These chips include two functional types—a preregulator module (PRM) and a voltage transformation module (VTM). The PRM takes an unregulated high-voltage bus, such as the 48-V bus found in telecom systems, and produces a regulated output at or near the nominal value of the input voltage. This regulated supply is called the factorized power bus. The VTM steps this bus voltage up or down with isolation to produce the voltage required at the load (Fig. 1).
The PRM and VTM may be operated open loop and still maintain a well regulated output. However, the output voltage may also be fed back to a control input on the PRM, which will then adjust PRM output to ensure tighter load regulation. The PRM accepts minimum inputs as low as 1.5 V and maximum inputs up to 400 V dc. But in practice, the input to an individual PRM is limited to a 5:1 voltage range within these extremes. The PRM's output, which is regulated but nonisolated, can assume a value from 0.5 V up to 400 V.
The PRM's input range accounts for 48-V battery-backed telecom systems, but it also covers the high-voltage dc output of an ac rectifier. When the input voltage is restricted to a 2:1 range, the PRM's conversion efficiency is 97% to 99%. A single PRM delivers as much as 200 W at 48 V dc.
Meanwhile, the VTM accepts a similarly wide range of voltages, in this case 2 to 400 V dc, and generates outputs from 0.5 to 400 V dc. In practice, the input voltage of a particular VTM is limited to a 2:1 range. In stepping up or down the factorized bus voltage, a single VTM provides 200 W or 80 A of output with a typical conversion efficiency of 92% to 96% or higher. This high efficiency is attributed to the part's high 3.5-MHz switching frequency. More detailed descriptions of FPA's underlying technology will be released later in the year.
Overall efficiency of the PRM-VTM combination from rectified ac input to low-voltage dc-output typically ranges from just below 90% to 95%. But under full-load conditions, it's possible to achieve overall efficiency exceeding 95%.That capability combined with the 0.846- by 1.260- by 0.236-in. BGA packaging of the two V•I Chips allows an FPA system to achieve power densities on the order of 400 W/in.3 Moreover, because the PRM produces a relatively high-voltage bus, which can be distributed with minimal I2R losses, the PRM may be mounted away from the load on a different pc board. At the point of load (POL), only the VTM need be present. Consequently, the POL power density can exceed 800 W/in.3
Those power densities reflect on-board mounting of the V•I Chips. In-board mounting options enable system-level power densities in excess of 500 W/in.3 and a POL power density greater than 1000 W/in.3 The latter value translates to a current density of nearly 500 A/in.3