Economical Flyback Converter Operates Off -48 V

When calculating the diodes' voltage requirements, the same voltage-divider scheme applies. When Q2 is conducting, the voltage is applied from ground to —48 V. The windings form a voltage divider, much the same as a resistance divider. With a maximum input voltage of −60 V, the voltage D5 must be able to block is equal to:

V_D5 = 10.6 V − [−60 × (9 + 6)/(9 + 9 + 6)] = 48 V

and for D3:

VD3 = 7 V − [−60 × (9/24)] = 29.5 V

So, D3 can be a low-cost Schottky diode.

The converter achieves regulation by closing the feedback loop around the output with the highest power. With good transformer design, adequate coupling can be achieved on other outputs as well. If tighter regulation is desired, a linear regulator can be added to the outputs. The 10-V output is sensed through pnp transistor Q4, which acts as a level shifter. Q3, which can be a pnp transistor connected as a diode, compensates for Q4's V_BE temperature coefficient, providing a temperature-compensated output. The present design can operate from −65°C to 80°C.

The current in R6 is equal to:

I_R6 = (V_10V/R6) + V_BE − V_BE = V_10V/R6

This current is reflected in Q4's collector (ignoring negligible base current). R6 is selected for 1 mA of collector current, so the voltage at the feedback pin (FB) of the controller chip becomes:

V_FB = (V_10V/R6) × 1.24k

which equals the 1.25-V reference at the error-amplifier input when the desired regulation is achieved. Q4 must be rated to sustain a V_CE equal to maximum input voltage plus the output voltage.

Figure 2 shows the waveforms at the transformer windings with respect to output ground. Using the turns ratio in a voltage-divider mode and per scope measurements of the 10-V winding, the voltage on Q2's drain flies up to:

V_DRAIN × (T1-2 + T2-6)/(total turns) = 13 V

V_DRAIN = 13 × {24/(6 + 9)} = 20.8 V

This agrees with the peak positive drain voltage on scope Ch 1. The drain goes to −48 V during Q2's on-time, since all the scope measurements are with respect to output ground and not the ground pin of the controller, which is −48 V.

Bootstrap And Startup: Since the −48-V supply provides the quiescent current for the controller IC and the current to drive the MOSFET gates, the bias current used by the chip at V_CC of 5 to 6 V imposes an excessive power loss. The 15 to 20 mA of current used for bias at 5 V can add an additional power loss of:

P_BIAS = (60 − 5) × 0.020 = 1.10 W

which is a significant percentage of the total output power. An additional winding can save this power by bootstrapping the bias supply once the PWM controller is on and the transformer voltages have been established. The cost of an additional winding is offset by the increase in efficiency.

The bootstrap operation works as follows. When power is first applied, Q1 turns on through the resistance divider R4 and R8, charging C3 through R5. Once the voltage on C3 exceeds 4.5 V, the PWM controller starts up, turning Q2 on and allowing current to flow through the transformer. Once the bootstrap power winding has enough voltage to turn on zener diode D6, Q5 will turn on. This action steals current away from the base at Q1 and turns Q1 off. The bias winding supplies a voltage that is approximately 6.5 V. Transistor Q1 must sustain the rail voltage of 60 V (max) and should be rated accordingly.

The SC1101, which can also be configured as a buck (step-down) controller, has the features to keep the flyback converter control loop simple. The dual-ground architecture allows for easy layout. The power ground (PGND) and the current-sense return CS(−) are referenced to the electrolytic input capacitor (C2) and Q2's source, while the GND pin is connected to the output dc return. The two grounds should be connected at the controller chip using a short connection.

The current-sense resistor (R13) limits the current in the primary on a pulse-by-pulse basis. It also acts as a soft-start resistor, charging the output capacitors and limiting the maximum current delivered to the secondary. This function prevents excessive current flow in the "coupled inductor" (the transformer), which could result in magnetic-core saturation.

There is no need for frequency compensation of the SC1101-based flyback converter, as long as some simple guidelines about the selection of external components and the parasitic parameters are observed. Flyback converters exhibit a loop phenomenon known as the right-half-plane (RHP) zero, which can lead to instabilities. In this circuit, the loop gain is designed to cross 0 dB at a frequency much lower than the RHP zero frequency. Typically, increasing the output capacitor size increases the margin for stability by lowering the LC pole frequency. The converter operates from an input of 30 to 60 V, with an efficiency of 92% at 60-V input and full load.

Finally, the transformer must be wound with judicious attention paid to leakage inductance to minimize voltage spikes on the MOSFET drain, as well as to improve coupling- and cross-regulation between windings. This reduces maximum voltage requirements for the MOSFET and snubbing requirements. Configuring the flyback converter's transformer as such by sharing the primary and secondary windings reduces the transformer's cost and complexity while improving coupling and regulation.