EDA Alert: February 18, 2003

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
February 18, 2003

=======================================

*************************ADVERTISEMENT***********************************
Complete your bench with Agilent Scopes
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07Lb0Aj

Agilent digital and analog oscilloscopes offer bandwidths from 60 MHz to
2.25 GHz and up to 16 MB deep memory. Mixed signal scopes seamlessly
integrate up to 20 channels. Also check out Agilent's function & pulse
generators to complete your design bench. Selection guide, specifications
and application notes.
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07Lb0Aj
*************************************************************************

Today's Table of Contents:
1. Viewpoint Exclusive -- Is There Any Future For ASIC Emulators?
2. Equivalence Checking Tool Targets Embedded Memories
3. ST Micro Taps Cadence's First Encounter for 90-nm SoC Design
4. Joint Effort Focuses On Communication-System Validation
5. Configurable DSP Core Targets Low-End SoCs
6. Ansoft's Power Tools Get An Upgrade
7. Happenings
- Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
- DATE 03
- 12th Synopsys Users Group (SNUG) Europe Conference
- 13th Synopsys Users Group (SNUG) San Jose Conference
- 40th Design Automation Conference
- EuroDesignCon 2003

************
1. Viewpoint - Exclusive to EDA Alert
************
Is there any future for ASIC emulators?
(or How FPGA-Based Prototypes Can Replace ASIC Emulators)

By Lauro Rizzatti, Marketing Vice President, Emulation & Verification
Engineering (EVE)

2002 was a tough year, for the worldwide economy and for EDA. No sector
suffered more than the ASIC emulation business. But blaming the economy for
the decline of the ASIC emulation market would be simply myopic.

For all the promises of ease of use, ASIC emulation systems have been
doomed by high cost and poor performance. Typically built on arrays of
hundreds, if not thousands, of FPGA devices, and mounted on many boards
linked through expensive backplanes, traditional emulation systems selling
in the million-dollar range have sacrificed the level of performance for
ease of use.

But the time for the ASIC emulator is over. Indeed, the latest generation
of FPGA devices, well represented by the Xilinx Virtex-II family, offers a
viable alternative for creating inexpensive FPGA-based prototypes by virtue
of their vast capacity and exceptional built-in features.

Yet, FPGA-based prototypes are difficult to set up and they don't support
debugging of hardware designs. Some design teams spend nine months or more
debugging the FPGA-based prototype of a fairly simple design of 1 million
ASIC gates, even when using off-the-shelf prototyping systems.

Clearly, there's a need for a new type of emulator to debug FPGA-based
prototypes. Such an emulator should have capabilities similar to those of
an ASIC emulator, be affordable, and possess nonintrusive resources to
debug the actual FPGA implementation of the design.

This FPGA-based prototype emulator could serve to apply a software
testbench to the FPGA implementation of the design. At the same time, it
could provide the means to read/write its memories and capture the internal
state of the design in a software simulation environment.
Further, this new tool ought to enable the connection to hardware models
(cores) when simulation models aren't available. The obvious corollary is
that if this system could also perform at tens of megahertz, there would be
no need anymore for the home-brewed FPGA-based prototypes.

Contact the author directly at:
mailto:lauro@eve-team.com

*******
2. News
*******
Equivalence Checking Tool Targets Embedded Memories

According to the Semiconductor Industry Association, memory now consumes
52% of the die area in SoC designs and will chew up 71% by 2005. Yet,
current functional memory verification approaches take far too long and
provide incomplete coverage.

Addressing that problem, the Conformal MEM equivalence checking tool closes
the gap between high-level system verification and implementation
verification at the transistor level. It uses functional recognition
analysis algorithms to automatically abstract higher-level models from
Spice or switch-level Verilog netlists. The tool relies on rigorous methods
to exhaustively determine if an RTL model is functionally equivalent to its
implementation. This vectorless approach can quickly dig out bugs that
older, simulation-based approaches may fail to detect.

The tool is shipping now for HP-Unix, Solaris, and Linux platforms. The
annual cost of a three-year, time-based license is $125,000.

Verplex Systems ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oP0A1

*******
3. News
*******
STMicro Taps Cadence's First Encounter for 90-nm SoC Design

STMicroelectronics will look to Cadence's First Encounter platform for
silicon virtual prototyping of its SoC designs at 90- and 130-nm silicon
geometries. At nanometer geometries, interconnect plays a vital role in
determining chip performance. ST design engineers will use First Encounter
to quickly generate and refine an accurate virtual prototype of their IC
physical design, including its interconnect. The prototype provides fast
feedback on chip performance and a fully functional, physically feasible
layout. This, in turn, will help ST's design teams produce a
signoff-quality floorplan and preliminary placement optimized for fast,
reliable design closure.

"Our evaluations indicated the First Encounter approach has clear
advantages, especially at nanometer geometries," says Philippe Magarshack,
group vice president for Design Automation, Central Research and
development at STMicroelectronics. "The silicon virtual prototype produces
realistic views of the chip in a shorter time than other methods we've
seen, significantly speeding up the physical design flow."

Cadence ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oQ0A2

*******
4. News
*******
Joint Effort Focuses On Communication System Validation

To improve pre-silicon prototyping and electronic system design
validation for communications designers, Aptix Corp. is offering Zaiq
Technology’s Pre-Configured Reusable Environment for testing Platform
(PREP) and SYSTEMware Component (SVC) Libraries to its customers.

The product combination permits Aptix customers to validate their
FPGA-based pre-silicon prototypes based on Aptix products at the
transaction level using Zaiq's validation platform and validation
intellectual property (IP). With an Aptix pre-silicon prototype, customers
can apply Zaiq validation IP to an FPGA-based design prototype. Because
validation is performed at the transaction level, the validation process
speeds up dramatically.

Products offered under the agreement include the PREP platform and SVC
component library. It provides chip and system designers with a
pre-fabricated verification environment for complex designs, along with a
methodology to comprehensively and efficiently test those designs. The SVC
Component Library includes Ethernet, SPI-4, SPI-5, PCI, PCIX, CSIX, SFI-4,
SFI-5, Optical Channel Bundle, and Packet Over SONET. Components will be
made available incrementally, with first deliveries in Q2 2003.
Pricing begins at $60,000 for a one-year term license for the PREP Platform
and one SVC Component.

Aptix ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK062f0AM
Zaiq ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oR0A3

*******
5. News
*******
Configurable DSP Core Targets Low-End SoCs

Despite its compact design, the APE2 configurable DSP core aspires to a new
price/performance benchmark for low-end SoC/ASIC applications. The core,
developed by Cambridge Consultants, can be implemented for 16-bit
applications with as few as 7000 gates. In addition, a novel adaptive
datapath architecture delivers high computational throughput.

Advanced application-specific performance is achieved by allowing users to
configure and customize the core's VLIW (very long instruction word)
processing architecture, together with a highly parallel structure
featuring dynamic datapath routing. Processors may easily be configured to
perform 10 parallel operations per cycle, for instance, delivering 1-BOPS
throughput at a 100-MHz clock rate in a very small silicon area.

Typical applications for the APE2 core include highly integrated
software-defined radios, integrated sensor systems, and audio processing
for markets such as consumer appliances, toys, and industrial
instrumentation. APE2 project implementation licenses are available for
single or multiple uses. Contact Cambridge for pricing.

Cambridge Consultants ==>
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oS0A4

*******
6. News
*******
Ansoft Power Tools Get An Upgrade

The Simplorer Power Suite now offers an integrated package that
addresses the rapidly increasing demand for smaller, more reliable power
designs in automotive, aerospace, and industrial automation.

Developed by Ansoft, the suite combines an enhanced version of SIMPLORER,
Ansoft's system simulation software, and PExprt, a modeling tool that
allows engineers to quickly evaluate thousands of possible designs and
accurately predict the performance of magnetic components. It boosts the
functionality of both SIMPLORER and PExprt.

SIMPLORER now includes:
- Enhanced dc and small-signal ac simulation capabilities
- Nonlinear ferrite-core modeling capability
- Various semiconductor and IC models
- Spice compatibility

PExprt now includes:
- Foil conductors and square and twisted wire types
- Generation of nonlinear component models for transformers and inductors,
complete with current, voltage, and power as output parameters for direct
import into SIMPLORER

The suite also includes a new library containing frequently used dc-dc
converter and other power-electronic topologies. The models are available
as switching and averaged versions that support different levels of
analysis.

The SIMPLORER Power Suite consists of SIMPLORER, PExprt, and the Switch
Mode Power Supply library. The suite was developed in conjunction with the
Electronic Engineering Division of the Universidad Politécnica de Madrid,
Spain.

Pricing for the suite starts at $14,900. It's available now.

Ansoft ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oT0A5

*************
7. Happenings
*************
Design and Verification Conference and Exhibition (DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, Calif.
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oU0A6

DATE 03
International Congress Centre, Munich, Germany
March 3-7, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK0paO0Ai

12th Synopsys Users Group (SNUG) Europe Conference
International Congress Centre, Munich, Germany
March 6-7, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07bm0AI

13th Synopsys Users Group (SNUG) San Jose Conference
Doubletree Hotel, San Jose, Calif.
March 17-19, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07bm0AI

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK0paP0Aj

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oV0A7

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
February 18, 2003

=======================================

*************************ADVERTISEMENT***********************************
Complete your bench with Agilent Scopes
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07Lb0Aj

Agilent digital and analog oscilloscopes offer bandwidths from 60 MHz to
2.25 GHz and up to 16 MB deep memory. Mixed signal scopes seamlessly
integrate up to 20 channels. Also check out Agilent's function & pulse
generators to complete your design bench. Selection guide, specifications
and application notes.
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07Lb0Aj
*************************************************************************

Today's Table of Contents:
1. Viewpoint Exclusive -- Is There Any Future For ASIC Emulators?
2. Equivalence Checking Tool Targets Embedded Memories
3. ST Micro Taps Cadence's First Encounter for 90-nm SoC Design
4. Joint Effort Focuses On Communication-System Validation
5. Configurable DSP Core Targets Low-End SoCs
6. Ansoft's Power Tools Get An Upgrade
7. Happenings
- Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
- DATE 03
- 12th Synopsys Users Group (SNUG) Europe Conference
- 13th Synopsys Users Group (SNUG) San Jose Conference
- 40th Design Automation Conference
- EuroDesignCon 2003

************
1. Viewpoint - Exclusive to EDA Alert
************
Is there any future for ASIC emulators?
(or How FPGA-Based Prototypes Can Replace ASIC Emulators)

By Lauro Rizzatti, Marketing Vice President, Emulation & Verification
Engineering (EVE)

2002 was a tough year, for the worldwide economy and for EDA. No sector
suffered more than the ASIC emulation business. But blaming the economy for
the decline of the ASIC emulation market would be simply myopic.

For all the promises of ease of use, ASIC emulation systems have been
doomed by high cost and poor performance. Typically built on arrays of
hundreds, if not thousands, of FPGA devices, and mounted on many boards
linked through expensive backplanes, traditional emulation systems selling
in the million-dollar range have sacrificed the level of performance for
ease of use.

But the time for the ASIC emulator is over. Indeed, the latest generation
of FPGA devices, well represented by the Xilinx Virtex-II family, offers a
viable alternative for creating inexpensive FPGA-based prototypes by virtue
of their vast capacity and exceptional built-in features.

Yet, FPGA-based prototypes are difficult to set up and they don't support
debugging of hardware designs. Some design teams spend nine months or more
debugging the FPGA-based prototype of a fairly simple design of 1 million
ASIC gates, even when using off-the-shelf prototyping systems.

Clearly, there's a need for a new type of emulator to debug FPGA-based
prototypes. Such an emulator should have capabilities similar to those of
an ASIC emulator, be affordable, and possess nonintrusive resources to
debug the actual FPGA implementation of the design.

This FPGA-based prototype emulator could serve to apply a software
testbench to the FPGA implementation of the design. At the same time, it
could provide the means to read/write its memories and capture the internal
state of the design in a software simulation environment.
Further, this new tool ought to enable the connection to hardware models
(cores) when simulation models aren't available. The obvious corollary is
that if this system could also perform at tens of megahertz, there would be
no need anymore for the home-brewed FPGA-based prototypes.

Contact the author directly at:
mailto:lauro@eve-team.com

*******
2. News
*******
Equivalence Checking Tool Targets Embedded Memories

According to the Semiconductor Industry Association, memory now consumes
52% of the die area in SoC designs and will chew up 71% by 2005. Yet,
current functional memory verification approaches take far too long and
provide incomplete coverage.

Addressing that problem, the Conformal MEM equivalence checking tool closes
the gap between high-level system verification and implementation
verification at the transistor level. It uses functional recognition
analysis algorithms to automatically abstract higher-level models from
Spice or switch-level Verilog netlists. The tool relies on rigorous methods
to exhaustively determine if an RTL model is functionally equivalent to its
implementation. This vectorless approach can quickly dig out bugs that
older, simulation-based approaches may fail to detect.

The tool is shipping now for HP-Unix, Solaris, and Linux platforms. The
annual cost of a three-year, time-based license is $125,000.

Verplex Systems ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oP0A1

*******
3. News
*******
STMicro Taps Cadence's First Encounter for 90-nm SoC Design

STMicroelectronics will look to Cadence's First Encounter platform for
silicon virtual prototyping of its SoC designs at 90- and 130-nm silicon
geometries. At nanometer geometries, interconnect plays a vital role in
determining chip performance. ST design engineers will use First Encounter
to quickly generate and refine an accurate virtual prototype of their IC
physical design, including its interconnect. The prototype provides fast
feedback on chip performance and a fully functional, physically feasible
layout. This, in turn, will help ST's design teams produce a
signoff-quality floorplan and preliminary placement optimized for fast,
reliable design closure.

"Our evaluations indicated the First Encounter approach has clear
advantages, especially at nanometer geometries," says Philippe Magarshack,
group vice president for Design Automation, Central Research and
development at STMicroelectronics. "The silicon virtual prototype produces
realistic views of the chip in a shorter time than other methods we've
seen, significantly speeding up the physical design flow."

Cadence ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oQ0A2

*******
4. News
*******
Joint Effort Focuses On Communication System Validation

To improve pre-silicon prototyping and electronic system design
validation for communications designers, Aptix Corp. is offering Zaiq
Technology’s Pre-Configured Reusable Environment for testing Platform
(PREP) and SYSTEMware Component (SVC) Libraries to its customers.

The product combination permits Aptix customers to validate their
FPGA-based pre-silicon prototypes based on Aptix products at the
transaction level using Zaiq's validation platform and validation
intellectual property (IP). With an Aptix pre-silicon prototype, customers
can apply Zaiq validation IP to an FPGA-based design prototype. Because
validation is performed at the transaction level, the validation process
speeds up dramatically.

Products offered under the agreement include the PREP platform and SVC
component library. It provides chip and system designers with a
pre-fabricated verification environment for complex designs, along with a
methodology to comprehensively and efficiently test those designs. The SVC
Component Library includes Ethernet, SPI-4, SPI-5, PCI, PCIX, CSIX, SFI-4,
SFI-5, Optical Channel Bundle, and Packet Over SONET. Components will be
made available incrementally, with first deliveries in Q2 2003.
Pricing begins at $60,000 for a one-year term license for the PREP Platform
and one SVC Component.

Aptix ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK062f0AM
Zaiq ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oR0A3

*******
5. News
*******
Configurable DSP Core Targets Low-End SoCs

Despite its compact design, the APE2 configurable DSP core aspires to a new
price/performance benchmark for low-end SoC/ASIC applications. The core,
developed by Cambridge Consultants, can be implemented for 16-bit
applications with as few as 7000 gates. In addition, a novel adaptive
datapath architecture delivers high computational throughput.

Advanced application-specific performance is achieved by allowing users to
configure and customize the core's VLIW (very long instruction word)
processing architecture, together with a highly parallel structure
featuring dynamic datapath routing. Processors may easily be configured to
perform 10 parallel operations per cycle, for instance, delivering 1-BOPS
throughput at a 100-MHz clock rate in a very small silicon area.

Typical applications for the APE2 core include highly integrated
software-defined radios, integrated sensor systems, and audio processing
for markets such as consumer appliances, toys, and industrial
instrumentation. APE2 project implementation licenses are available for
single or multiple uses. Contact Cambridge for pricing.

Cambridge Consultants ==>
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oS0A4

*******
6. News
*******
Ansoft Power Tools Get An Upgrade

The Simplorer Power Suite now offers an integrated package that
addresses the rapidly increasing demand for smaller, more reliable power
designs in automotive, aerospace, and industrial automation.

Developed by Ansoft, the suite combines an enhanced version of SIMPLORER,
Ansoft's system simulation software, and PExprt, a modeling tool that
allows engineers to quickly evaluate thousands of possible designs and
accurately predict the performance of magnetic components. It boosts the
functionality of both SIMPLORER and PExprt.

SIMPLORER now includes:
- Enhanced dc and small-signal ac simulation capabilities
- Nonlinear ferrite-core modeling capability
- Various semiconductor and IC models
- Spice compatibility

PExprt now includes:
- Foil conductors and square and twisted wire types
- Generation of nonlinear component models for transformers and inductors,
complete with current, voltage, and power as output parameters for direct
import into SIMPLORER

The suite also includes a new library containing frequently used dc-dc
converter and other power-electronic topologies. The models are available
as switching and averaged versions that support different levels of
analysis.

The SIMPLORER Power Suite consists of SIMPLORER, PExprt, and the Switch
Mode Power Supply library. The suite was developed in conjunction with the
Electronic Engineering Division of the Universidad Politécnica de Madrid,
Spain.

Pricing for the suite starts at $14,900. It's available now.

Ansoft ==> http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oT0A5

*************
7. Happenings
*************
Design and Verification Conference and Exhibition (DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, Calif.
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oU0A6

DATE 03
International Congress Centre, Munich, Germany
March 3-7, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK0paO0Ai

12th Synopsys Users Group (SNUG) Europe Conference
International Congress Centre, Munich, Germany
March 6-7, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07bm0AI

13th Synopsys Users Group (SNUG) San Jose Conference
Doubletree Hotel, San Jose, Calif.
March 17-19, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07bm0AI

40th Design Automation Conference
Anaheim Convention Center, Anaheim, Calif.
June 2-6, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK0paP0Aj

EuroDesignCon 2003
Arabella Sheraton Grand Hotel, Munich, Germany
October 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo/y/ePcD0DJhFR0BSK07oV0A7

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

=========================

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe, send a blank e-mail to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe, send a blank e-mail to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://www.planetee.com/

===============================
Copyright 2003 Penton Media Inc.