It's now common for FPGA-based boards to require as many as four or five different low-voltage supplies to power the various components.
First it was 3.3 V, then 2.5 V, 1.8 V, 1.5 V, and now 1.2 V. Each new FPGA generation seems to require a new low supply voltage.
On top of that, new communications and memory technologies (such as DDR Memory and DDR-2) require additional new I/O supply voltages and termination voltages. Now, FPGA-based boards frequently demand four or five different low voltages to power the various components.
At the same time, increased CMOS gate counts and higher clock speeds have resulted in higher power requirements. For example, Altera offers 14 different products in its Stratix/Stratix GX family of FPGAs. In terms of power required, the smallest FPGA clocking under 100 MHz will need less than 1.5 W of peak power for the core logic, whereas the largest version will need almost 21 W for the core logic when clocked at 300 MHz.1
These trends are forcing board designers to use more and higher-performance power supplies. Fortunately, the latest generation of low-voltage power-management ICs is keeping pace with the challenges presented by these high-performance boards.2
LATEST-GENERATION FPGA POWER REQUIREMENTS
A large part of the value of FPGAs is their flexibility. For example, the Stratix/Stratix GX family mentioned above ranges in functionality from 10,570 logic elements (LEs) to over 79,000 LEs.3 The number of LEs and other internal blocks used simultaneously determines the peak gate usage. Along with the switching frequency and operating voltage, this sets the peak power consumption, which depends heavily on the total system requirements. All major FPGA vendors have online "power estimators" that let customers describe their designs in terms of blocks used and switching frequency and use these inputs to calculate the expected power-supply current and power consumed.
FPGA-based board designers face the uncertainty about the system's actual power requirements because the gate-level design typically isn't finalized before the hardware is first generated. (The flexibility of FPGAs allows this, so engineers should take advantage of it!) Another major issue for power-supply designers involves dynamic load requirements, or transient performance. The FPGA load may quickly go from an inactive, low-current state to a fully processing state or vice versa, and accurate regulation needs to be maintained. Transient conditions like this one typically aren't a part of the company's power calculators, so the board designer must make estimates of worst-case transients and design the power-supply circuit accordingly.
Core Logic Power:
In large FPGAs, the logic core generally has the most demanding current requirements—up to tens of amperes, depending on the number of gates being used and the clock frequency. On the positive side, once the FPGA family is selected, the core logic supply voltage is set (as shown in the table, for example). This core logic supply is designated VCCINT by both Xilinx and Altera.
Maximum current estimates can be found in FPGA power application guides or calculated using the online power estimators. These maximum current estimates let the hardware engineer design a power supply that will be sufficient for the design, even if the block usage and design in the FPGA hasn't been finalized.
I/O Power:
In the latest generation of FPGAs, over 15 different I/O standards are offered with various required voltage levels. However, usually 1.5, 1.8, 2.5, or 3.3 V is required, depending on the I/O standard. Because I/O standards can be set independently by the I/O block in the FPGA, more than one I/O voltage for a single FPGA is possible. I/O current requirements depend on the number of I/Os used and the clocking speed.
Generally, even in the largest FPGAs, I/O currents are less than 3 A (which, given the generally higher voltage than the core logic, may still be up to 10 W of power). Because the I/O voltages required by an FPGA are determined by the devices that interface with the FPGA, often the supply generated for the FPGA's I/O can be shared to power the I/O of the companion device and possibly other circuits.
VAUX Power: The "auxiliary" supply is important for the latest generation of Xilinx FPGAs because it's tied into the JTAG, DCM, and other circuitry. It's designated VCCAUX and is usually 2.5 or 3.3 V. VCCAUX must be sufficiently decoupled to avoid power-supply transients coupling into the FPGA's clock.
Due to these power requirements, the supply must generate at least one and often two or three voltages below 3.3 V. Typically, this means using a switching buck regulator or a linear regulator from a higher voltage bus (+3.3, +5, or +12 V are currently the most commonly available) down to the required low voltage.
But linear regulators are inherently inefficient because they drop the voltage across a variable resistor (the pass transistor). Therefore, the load current times the voltage drop equals the power dissipated in the device. At the current levels required by the newest generations of FPGAs, this also can generate large amounts of heat. In battery-powered systems, efficiency is typically the driving requirement for using a switching regulator instead of a linear regulator. In wall-powered systems, heat considerations usually move designers to use switchers instead of linears.