Finally, the minimum output capacitance required for the design is calculated. The ESRMAX value calculated previously and the minimum output capacitance value dictate the type and minimum number of output capacitors needed to meet the voltage-tolerance specifications and transient response. The minimum output capacitance for this design is 324 µF:
COUT MIN = [LOUT X (current step)2]/[(voltage window − ripple + VOUT)2 − VOUT2] (5)
Based on these requirements, one Panasonic EEFUE0D391R (12 mÙ, 390 µF) specialty polymer aluminum electrolytic chip capacitor supports these requirements. Refer to the ISL6521 datasheet for instructions on the PWM controller compensation.
The final piece of the component-selection puzzle is power MOSFET selection. Power dissipation and package selection drive this process. Conduction loss and switching loss compose power dissipation. These losses are distributed between the upper and lower MOSFETs, according to the duty cycle.
The conduction losses make up the main component of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The ISL6521 datasheet supplies equations to calculate these losses. Other selection criteria include package size, which affects both board area and height off the board. Typically, an eight-lead SOIC package will support the power, cost, and space limitations in 10-A or lower designs.
Power-device selection for the linear portions of the controller IC is driven mainly by RDS(ON), current gain, and thermal considerations. The internal drivers can provide up to 120 mA of load current without an external pass device. Based on this current drive capability, external bipolar npn transistors can support loads of up to 3 A. The main criterion for choosing transistors is package selection for efficient heat removal. The power dissipated in a linear regulator is:
PowerLinear = IOUT X (VIN − VOUT) (6)
Select a package that maintains the junction temperature below the package rating with a maximum expected ambient temperature. The current gain at a given operating VCE must be sufficiently large to provide the desired maximum output load current when the base is fed with the minimum driver output current of 100 mA.
LAYOUT RECOMMENDATIONS
Layout is a crucial factor in on-board switching-power-supply design. With power devices switching efficiently at greater than 200 kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress.
Careful component layout and pc-board design help suppress the voltage spikes in the converters. As an example, consider the turn-off transition of the upper PWM MOSFET. Prior to turn-off, the MOSFET carries the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short but wide traces minimize the magnitude of voltage spikes.
A switching dc-dc converter has two sets of critical components. The switching components (power FETs and inductors) are the most critical because they switch large amounts of energy, and therefore they tend to generate large amounts of noise. Next are the small-signal components that connect to sensitive nodes or supply critical bypass current and signal coupling.
Place the switching components close to the device first. Minimize the length of the connections between the input capacitor(s), CIN, and the output power switches (whether external with the ISL6521 or internal in the EL75xx family) by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible.
The critical small-signal components include any bypass capacitors, feedback components, and compensation components. The feedback resistors should be located as close as possible to the relevant FB pin, with vias tied straight to the ground plane as needed.
Finally, a multilayer pc board is recommended. Dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Make sure that the metal runs are short from the PHASE or LX terminals to the output inductor.
The wiring traces from the GATE pins on the ISL6521 to the MOSFET gates also should be kept short, and they should be wide enough to easily handle the 1 A of drive current. The power plane should support the input- and output-power nodes. Use copper-filled polygons on the top and bottom circuit layers for the phase nodes. For small signal wiring, use the remaining printed circuit.
A SMALLER SOLUTION
The technology for high-performance switching dc-dc power supplies has progressed dramatically in the past few years. It's now possible to purchase devices that require only a few external components (usually an inductor, a few capacitors, and a few resistors) to generate a well-regulated, highly efficient supply voltage. Often, these ICs also include features such as overvoltage protection, supply sequencing capabilities, and soft-start.
One example is the EL75xx switching dc-dc power supply family, which can supply between 0.6 and 8 A of output current. The EL75xx family can convert down from VIN = 3.0 to 6 V, to as low as 0.8 V for VOUT. This covers all major FPGA-core and I/O voltage levels. The design shown in Figure 2 can implement up to a 25-W supply in less than 0.72 in.2
A 1-A output supply (approximately 4 W max) can be created from another member of the family, the EL7531, in 0.18 in.2 This family of ICs achieves efficiencies as high as 95%. Some, including the EL7531, have a pulse-frequency-modulation (PFM) mode that can be used for "light" loads to keep efficiency above 75% even down to low output-current levels (e.g., 10 mA) under most conditions.
COMPONENT SELECTION
By integrating the power FETs and the compensation/feedback circuitry, power supplies built with products like the EL753x simplify the design task and minimize the required board area. In exchange, the customer has less flexibility to tailor the feedback compensation to optimize performance for a given system.
Output Inductor: Because of the EL753x's internal compensation, the range of allowable inductors is relatively narrow. For the EL753x family, an inductor value of 1.5 to 4.7 µH is recommended. This small inductor value is critical to minimizing the total board space of the power supply and is a direct result of the high-frequency switching inside the EL753x. Selecting the output inductor is also heavily influenced by the required transient response of the supply, as discussed in the ISL6521 equations above.
I/O Capacitors: The EL753x requires a minimum 4.7 µF to ensure proper and stable operation during extreme load and temperature conditions; the recommended I/O capacitance is 10 µF. Selecting the type of capacitor is especially important to maintain the required performance over temperature. For example, a Y5V capacitor loses its ability to store charge by up to 50% at −40°C and 85°C, while an X5R's and an X7R's capacitance is a weaker function of temperature. These types of dielectrics are the best candidates for most applications.
References:
- Source: Altera Stratix Power Calculator online.
- Refer to www.intersil.com/data/AG for Applications Guide for Powering Xilinx FPGAs and DDR Memory, Applications Guide for Powering Altera FPGAs and DDR Memory, and Applications Guide for Powering Actel FPGAs and DDR Memory.
- Source: www.altera.com/products/devices.
Finally, the minimum output capacitance required for the design is calculated. The ESRMAX value calculated previously and the minimum output capacitance value dictate the type and minimum number of output capacitors needed to meet the voltage-tolerance specifications and transient response. The minimum output capacitance for this design is 324 µF:
COUT MIN = [LOUT X (current step)2]/[(voltage window − ripple + VOUT)2 − VOUT2] (5)
Based on these requirements, one Panasonic EEFUE0D391R (12 mÙ, 390 µF) specialty polymer aluminum electrolytic chip capacitor supports these requirements. Refer to the ISL6521 datasheet for instructions on the PWM controller compensation.
The final piece of the component-selection puzzle is power MOSFET selection. Power dissipation and package selection drive this process. Conduction loss and switching loss compose power dissipation. These losses are distributed between the upper and lower MOSFETs, according to the duty cycle.
The conduction losses make up the main component of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The ISL6521 datasheet supplies equations to calculate these losses. Other selection criteria include package size, which affects both board area and height off the board. Typically, an eight-lead SOIC package will support the power, cost, and space limitations in 10-A or lower designs.
Power-device selection for the linear portions of the controller IC is driven mainly by RDS(ON), current gain, and thermal considerations. The internal drivers can provide up to 120 mA of load current without an external pass device. Based on this current drive capability, external bipolar npn transistors can support loads of up to 3 A. The main criterion for choosing transistors is package selection for efficient heat removal. The power dissipated in a linear regulator is:
PowerLinear = IOUT X (VIN − VOUT) (6)
Select a package that maintains the junction temperature below the package rating with a maximum expected ambient temperature. The current gain at a given operating VCE must be sufficiently large to provide the desired maximum output load current when the base is fed with the minimum driver output current of 100 mA.
LAYOUT RECOMMENDATIONS
Layout is a crucial factor in on-board switching-power-supply design. With power devices switching efficiently at greater than 200 kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress.
Careful component layout and pc-board design help suppress the voltage spikes in the converters. As an example, consider the turn-off transition of the upper PWM MOSFET. Prior to turn-off, the MOSFET carries the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short but wide traces minimize the magnitude of voltage spikes.
A switching dc-dc converter has two sets of critical components. The switching components (power FETs and inductors) are the most critical because they switch large amounts of energy, and therefore they tend to generate large amounts of noise. Next are the small-signal components that connect to sensitive nodes or supply critical bypass current and signal coupling.
Place the switching components close to the device first. Minimize the length of the connections between the input capacitor(s), CIN, and the output power switches (whether external with the ISL6521 or internal in the EL75xx family) by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible.
The critical small-signal components include any bypass capacitors, feedback components, and compensation components. The feedback resistors should be located as close as possible to the relevant FB pin, with vias tied straight to the ground plane as needed.
Finally, a multilayer pc board is recommended. Dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Make sure that the metal runs are short from the PHASE or LX terminals to the output inductor.
The wiring traces from the GATE pins on the ISL6521 to the MOSFET gates also should be kept short, and they should be wide enough to easily handle the 1 A of drive current. The power plane should support the input- and output-power nodes. Use copper-filled polygons on the top and bottom circuit layers for the phase nodes. For small signal wiring, use the remaining printed circuit.
A SMALLER SOLUTION
The technology for high-performance switching dc-dc power supplies has progressed dramatically in the past few years. It's now possible to purchase devices that require only a few external components (usually an inductor, a few capacitors, and a few resistors) to generate a well-regulated, highly efficient supply voltage. Often, these ICs also include features such as overvoltage protection, supply sequencing capabilities, and soft-start.
One example is the EL75xx switching dc-dc power supply family, which can supply between 0.6 and 8 A of output current. The EL75xx family can convert down from VIN = 3.0 to 6 V, to as low as 0.8 V for VOUT. This covers all major FPGA-core and I/O voltage levels. The design shown in Figure 2 can implement up to a 25-W supply in less than 0.72 in.2
A 1-A output supply (approximately 4 W max) can be created from another member of the family, the EL7531, in 0.18 in.2 This family of ICs achieves efficiencies as high as 95%. Some, including the EL7531, have a pulse-frequency-modulation (PFM) mode that can be used for "light" loads to keep efficiency above 75% even down to low output-current levels (e.g., 10 mA) under most conditions.
COMPONENT SELECTION
By integrating the power FETs and the compensation/feedback circuitry, power supplies built with products like the EL753x simplify the design task and minimize the required board area. In exchange, the customer has less flexibility to tailor the feedback compensation to optimize performance for a given system.
Output Inductor: Because of the EL753x's internal compensation, the range of allowable inductors is relatively narrow. For the EL753x family, an inductor value of 1.5 to 4.7 µH is recommended. This small inductor value is critical to minimizing the total board space of the power supply and is a direct result of the high-frequency switching inside the EL753x. Selecting the output inductor is also heavily influenced by the required transient response of the supply, as discussed in the ISL6521 equations above.
I/O Capacitors: The EL753x requires a minimum 4.7 µF to ensure proper and stable operation during extreme load and temperature conditions; the recommended I/O capacitance is 10 µF. Selecting the type of capacitor is especially important to maintain the required performance over temperature. For example, a Y5V capacitor loses its ability to store charge by up to 50% at −40°C and 85°C, while an X5R's and an X7R's capacitance is a weaker function of temperature. These types of dielectrics are the best candidates for most applications.
References:
- Source: Altera Stratix Power Calculator online.
- Refer to www.intersil.com/data/AG for Applications Guide for Powering Xilinx FPGAs and DDR Memory, Applications Guide for Powering Altera FPGAs and DDR Memory, and Applications Guide for Powering Actel FPGAs and DDR Memory.
- Source: www.altera.com/products/devices.