Learn "The Rules Of The Game" For Powering Today's Processors

Sticking To The Budget
The main items in a V_core voltage tolerance budget are: V_transient, or positive and negative transient excursion; V_droop bus, caused by the voltage drop across the etch between the output caps and the processor; ripple voltage on the output caps caused by the inductor ripple current; "static regulation" of the voltage regulation module (VRM) control chip; and temperature effects.

Figure 4 shows an actual voltage budget, the various items that affect the processor voltage, and the advantages of using droop to achieve a tight operating-voltage window. As shown, droop improves the tolerance budget from ±5% or a total of 10%, to +5%/-2% for a total of 7% for this design.

To lower the output voltage as current increases, you need to measure the output current—and do so accurately over the system’s full current and temperature operating range. There are a number of ways to measure power-supply output current in a VRM. The table shows the most commonly used techniques and the advantages/disadvantages of each.

Multiple Phases, Multiple Challenges
Because today’s processors require more current than can be practically supplied by a single-phase VRM, multiple-phase VRM designs have become the standard approach for output currents over 25 A.

Going the multiple-phase route offers many advantages, including lower individual FET current, better thermal dissipation, and improved transient response. However, using multiple phases presents the new problem of how to balance the currents in the individual phases. When the phase currents aren’t well balanced, it can cause thermal problems and have a negative impact on VRM efficiency. Accurate current measurement of each phase is again critical, as it is in meeting the load line, to ensure proper phase current balance.

"On-The-Fly" VID
One final item that needs to be addressed is the dynamic voltage identification (VID) specification, sometimes called the VID on-the-fly specification. VID, a parallel digital word, tells the voltage regulator what to output. Dynamic VID allows the processor to save power by lowering its V_core voltage while running. This voltage change can be rather large, up to 450 mV, and has to be completed within certain time limits. Also, the current-limit set point must be considered: When going from a low to a high voltage, the VRM has to support the increased processor current plus the current going into the output capacitors to get the voltage to slew at the 2.5-mV/µs rate. Special consideration also needs to be taken when going from a high to a low voltage, because the processor current alone may not be able to discharge the output voltage fast enough.

Caution: Some VRM controllers don’t allow the output to sink current. Others that sink current can’t monitor the output current when it’s negative (sinking). This may be acceptable in lower-current applications. But it could cause instabilities and excessive undershoot when operating in this mode, especially at higher currents and fast load steps.

Selecting the right VRM controller is crucial to ending up with a stable, robust design while still meeting the aggressive performance required for proper operation of today’s processors. A number of questions should be asked when making a selection:

1. Will the final design be accurate enough to get the CPU power supplier’s approval? For example, Intel has currently approved only inductor-current sensing to set the load line, whereas some manufacturers are still using R_ds sensing.
2. Does the design require a narrow set of component values, or can a wider range of components be utilized so that you can use your own preferred components?
3. Is the chip versatile enough to be employed in a number of different applications? And is it accurate and flexible enough for use in future Intel processors and flexible-motherboard (FMB) designs? (Intel specifies an FMB power requirement that’s the maximum any processor in a family will require, now and in future releases.) Important parameters in this respect would be operating-frequency range, selectable number of phases, adjustable load line, etc.
4. Are the architectures proven, and do they have a good track record? Totally new architectures, while often exciting, carry additional risks and possible surprises. Can your project schedule support these risks?
5. What about support documentation and design tools for the controller? Is there sufficient information to understand how the chip works—and in enough detail—to make a solid design as well as help in debug and bring-up of the first board? Are the design tools intuitive enough to simplify the design process?
6. Finally, and most importantly, is the cost/performance of the final design acceptable? The lowest-cost implementation that doesn’t meet specifications isn’t a good tradeoff. And a high-performing design that puts the end product at a cost disadvantage won’t win praises from management. From a supply-chain standpoint, also consider the availability of alternate sources for the device.

Design Example
A good example of a well-balanced VRM10 control chip is the FAN5019 multiphase controller. The FAN5019 can be used in 2-, 3-, or 4-phase VRM10 applications. Figure 5 shows the schematic of a three-phase FAN5019 design.

As the design example shows, the FAN5019 uses a combination of bottom FET current sensing and inductor R_DC current sensing to take advantage of each approach. The FET current-sensing approach gives good current balance between phases. And the inductor current-sense circuit provides accurate setting of the output droop voltage to meet tight load-line requirements.

The FAN5019 controller exploits the best architectural trade-offs of the various schemes mentioned in this article. Its full data sheet includes a comprehensive, step-by-step design guide. An extensive Mathcad design file allows designers to easily optimize the design for their particular application with their selected components.

Additional benefits include the fact that it’s second-sourced, providing an alternate source for logistic planning. A companion device, the FAN5009 driver, is available in an MLP package. It offers the key advantage of higher power dissipation—a critical factor in higher frequency designs.