As 90-nm process technologies began
entering the mainstream a few years ago,
it became clear that device delays were no
longer the chief culprit. Interconnect
delays had caught and passed them,
becoming the number-one contributor to
timing woes.
Now as the 65-nm node is hitting its
stride, a parallel trend has arisen for designers in the power
domain. No longer is dynamic power consumption the dominant
factor in total power budgets. Rather, leakage power
dominates those budgets. That's power down the drain (pun
intended) that can't be used for greater performance. But
why is leakage power such a huge concern?
"For cell phones, manufacturers want standby power consumption
to be no more than 5% of the full operational power
consumption," says Dian Yang, general manager and vice
president of product management at Apache Design Systems.
"So if full power consumption is, say, 100 mW, standby power
can't be more than 5 mW. But at deep-submicron nodes, over
50% of total power consumption is lost to leakage."
Leakage is a fact of life for CMOS transistors. And what's
already a bad situation at 65 nm can get worse - much
worse - at 45 nm. Yet design techniques are available to help
mitigate the leakage situation. Upcoming materials and
process tweaks also hold promise.
Root causes
There are two primary sources of leakage
in MOS transistors (Fig. 1). One is the subthreshold leakage,
which is leakage from drain to source (or power to
ground). Subthreshold leakage is rising with each process
node and shows no sign of abating. The mechanics of subthreshold
leakage are based on the fact that no transistor is a
perfect switch.
"In digital logic we all think of them as perfect switches,
but they never really turn off completely," says Jerry Frenkil,
CTO and vice president of research and development at
Sequence Design.
The issue can be seen in terms of the three main regions of
operation for a transistor. There's the cutoff region, where current
is effectively zero. In the saturation region, the transistor
is completely on and can pump a lot of current. In the linear
region, the device essentially functions as a linear amplifier.
"Between the linear and cutoff regions, there's a weak
inversion current flowing between source and drain. The
transistor begins to invert, but it's in a sensitive region where
a small change in gate voltage results in a large change in
current," says Frenkil.
"The degree of change in the current is directly related to
how low the threshold voltage is. The drain current on a
transistor is a function of, among other things, the voltage on
the source, drain, and gate. You can't make that term in the
equation go completely to zero, so there's always a little bit
of current flowing," he adds.
The other main component of the overall leakage issue is
gate-oxide leakage (Fig. 1, again). Gate leakage (as it's commonly
known) is an unhappy byproduct of progress. Transistor
gates are composed of polysilicon sitting on silicon dioxide,
which has the advantage of being very easy to fabricate.
But as semiconductor processes have scaled downward, gate
lengths are obviously shorter. The downward scaling affects all
dimensions, so that silicon dioxide gate layer has become thinner as well to increase gate capacitance and thereby drive current.
Consequently, gate leakage manifests itself as electron
tunneling through the gate oxide.
Differentiating between these two primary sources of leakage
power is critical. While gate leakage is an issue that can,
and in all likelihood will, be solved with process and materials
improvements, subthreshold leakage is entirely a designrelated
problem in terms of any possible fixes.
"In the long run, designers have to worry about subthreshold
leakage but not gate leakage," says Frenkil. "At 65 nm,
there's no convenient process solution for gate leakage. But
at the smaller nodes, there will be."