Leveraging multicore
The
growing emphasis on multicore architectures
is an important trend to watch.
Anmol Mathur, chief technology officer
at Calypto Design, points out that leakage
is significantly reduced by moving
to multicore architectures.
"So far, most of the things done at
RTL and above are geared at reduction
of dynamic power," says Mathur. "Typically,
leakage is addressed more at
implementation using multi-VT cells
and other techniques."
But Mathur believes that the tide is
turning. "People are starting to think
about at RTL and at the architectural level.
They're taking it to a slightly higher
level of abstraction," he says.
The advantage of multicore architectures
with regard to leakage stems from
the breaking apart of a very power-hungry
function. "You have a fixed amount
of area on the chip," Mathur says.
"You can use a very fast single core,
with fast memories and caches, or you
can use that same real estate for, say,
four smaller cores, each at a lower frequency,
and get the same aggregate
throughput," he adds. Those four lower-
frequency cores enable scaling back
the power supply, reducing dynamic
power and leakage power.
Examination of power management
at the microarchitectural level is critical,
according to Mohit Bhatnagar of
Encounter product marketing at
Cadence Design Systems (Fig. 4). "At
65 nm, you have to answer questions,"
he says. "What is the range of techniques
I'm using? If I use power shutoff
switches, what is the range of voltage
domains I should use? Should I use my
foundry's generic process or their lowpower
process, compromising performance
but making power goals more
attainable?"
Equally important, says Bhatnagar, is
availing oneself of an automated flow for
these architectural explorations. "The
range of choices is very large. You don't
want to undertake this process manually,"
Bhatnagar says. Partitioning blocks
into various voltage domains might also
mean hierarchies within blocks with subblocks
at lower voltages.
What can you do to control sub-threshold
leakage when the chip is fully awake
and active? See "Control Leakage In
Active Mode" at www.electronicdesign.com, Drill Deeper 17400. Also, find out
how recent advances in materials can
help solve the gate-leakage problem in
"Materials Play A Key Role In Stopping
Leakage," Drill Deeper 17401.