Sleep Stages
The Core Duo processor can operate at very low voltages. Advanced techniques minimize clock and signal switching, which reduces power dissipation in the active state. The processor can quickly enter and exit from these states to save power while maintaining fast responsiveness. Low-power states comprise " stopgrant," "stop-grant snoop," "sleep," "deep sleep," "deeper sleep," and "deeper sleep low-voltage"(Fig. 2).
In the "stop-grant" state, snoops are serviced, and interrupts from the front-side bus (FSB) are latched. But only one of those interrupts will be serviced upon return to normal operation. The "stop-grant snoop" state is the response to a snoop. The core stays in this state until the snoop is serviced or an interrupt is latched.
In "sleep" state, internal clocks are shut down, and the core doesn't respond to snoops. But it does maintain context. "Deep sleep," a lower-power version of "sleep," eschews all transitions on the FSB. "Deeper sleep" reduces the core voltage. Two possible reduced levels exist. First, at the lower level, L2 cache is shut down and the state is called "deeper sleep low-voltage." Second, under some conditions, the processor can flush and disable a programmable number of L2 cache ways on each entry to the "deeper sleep" state.
Note that these explanations of the low-power states are very superficial, compared to the explanations in the datasheet. But they should provide a sense of the depth of low-power options available. For additional power savings, DDR2 memory self-refresh provides chip-set and dual-inline memory-module (DIMM) power savings by putting memory into a reduced power state when the display is still active on DDR2-based platforms.
Meanwhile, "dynamic bus parking" saves platform power by allowing the chip set to power down with the processor in its low-frequency powersaving states. Through "enhanced deeper sleep with dynamic cache sizing," the L2 smart cache can dynamically flush its ways to system memory based on demand or during periods of inactivity. Power savings occur as cache ways are turned off once the data is saved in memory.
L2 cache data integrity determines the "deeper sleep" minimum voltage limit for the processor. So once the dynamic cache sizing feature flushes the entire L2 cache to memory, the processor transitions to a new power-management state called "enhanced deeper sleep." In this state, the processor can lower its voltage below the deeper sleep minimum voltage.
Intel gave the Core Duo processor a new thermal-management system, the Advanced Thermal Manager. Each of the processor's cores features a digital temperature sensor and a thermal monitor. Located close to the hot spots on the chip, they enable more precise fan control. The processor also supports Intel's next-generation, dual-core optimized voltage regulator, Intel Mobile Voltage Positioning (Intel MVP VI).
A split-transaction, deferred reply protocol helps power-optimize the 667-MHz system bus. The system ( frontside) bus uses source-synchronous transfer (SST) for addresses and data. It transfers data four times per bus clock, and the address bus can deliver addresses twice per bus clock. Together, they provide a data-bus bandwidth of up to 5.33 Gbytes/s. Signal levels and timing consist of Advanced Gunning Transceiver Logic (AGTL+).
With all this, the new laptops will have as much battery life as their predecessors. But their power supplies still must support instantaneous demand.