Current trends in high-performance digital bus designs have pushed the synchronous data-acquisition speeds of high-end logic analyzers to their limits. Nevertheless, there remains a need to accurately capture state data at these extreme speeds. To accomplish that goal, today's digital designers must understand the challenges presented by high-performance bus designs. Among those challenges are the critical relationships between the setup and hold times of their device-under-test (DUT) and their logic analyzer, as well as the placement of the logic analyzer's sample position. This article examines the difficulties inherent in sampling high-performance buses with logic analyzers, and some strategies for addressing those difficulties, both manually and automatically.
Regardless of the approach used, one critical factor can't be ignored—the importance of setup and hold times. By definition, every synchronous digital circuit with both clock and data inputs will also have a setup-and-hold-time specification. As bus speeds continue to rise, it becomes increasingly important to understand exactly what this specification means in relation to the logic analyzer's ability to capture data when the DUT's signals are stable and not transitioning. This stable data region is referred to as the "data-valid window."
Before discussing these topics as they pertain to high-performance buses, it's a good idea to review the basic concepts at hand. The "setup time" is defined as the amount of time that the data must remain stable prior to a clock transition. It allows data at the inputs to become stable before being acted on by the gates. The "hold time" refers to the amount of time that the data must remain stable after a clock transition. It ensures that the gates will have enough time to act on the data. The sum of these two times is known as the "setup/hold window."
A logic analyzer operating in a synchronous sampling mode is no different from any synchronous circuit that it might be probing, as it too has a setup/hold window. The logic analyzer latches data appearing at its inputs on each active clock transition provided by the DUT, and this data must be stable for a specified time before and after the clock transition. To correctly sample data, the logic analyzer's setup/hold window must fit within the DUT's data-valid window (Fig. 1). Typically, the logic analyzer's sample position is in the center of its setup/hold window. Because the location of a data-valid window in relation to the bus clock may vary between different bus types, high-end logic analyzers let users adjust the position of their setup/hold window—relative to the sampling clock—in resolutions from 500 to 100 ps. This feature helps ensure an accurate measurement by placing the analyzer's setup/hold window and its sample position within the DUT's data-valid window.
When probing bus signals clocked at lower speeds (usually less than 200 MHz), the relationship between the DUT's setup/hold and data-valid windows and the logic analyzer's set-up/hold window and sample position normally aren't an issue. This is because the logic analyzer's setup/hold window is relatively small compared to the DUT's data-valid window. But today, logic-analyzer users frequently face the challenge of having to know where the boundaries of that data-valid window are in relation to the sampling clock edge. As bus speeds continue to increase, knowing the position of the data-valid window will determine a user's success at making logic-analyzer measurements.
High-Performance Bus Challenges
With computer and networking systems continuing to push performance limits to new heights, the current crop of bus designs runs at speeds that result in very narrow data-valid windows. In many cases, newer clocking schemes, such as double-edge and source-synchronous clocking, have replaced traditional clocking schemes. In fact, margins have tightened to the point that a single clock reference across all signals in a bus is often impractical. Some characteristics of today's high-performance memory buses and the challenges they present to traditional logic-analyzer usage include the following.
Double-edge clocking: Also known as double-data-rate clocking, double-edge clocking obtains twice the data-transfer rate by using each clock edge for data-transfer bursts to and from memory. The basic clock rate is given as the whole clock period. Setup and control transfers typically operate at this basic rate, although once set up, data transfers operate at twice the basic rate by using both clock edges (Fig. 2).
Timing margins for control transfers—that is, mode, address, etc.—are generous due to two factors. First, data transfers operate at twice the rate of control transfers. A logic analyzer able to run at the double-edge-clocked data rate is more than capable of tracking control transfers. Also, control transfers are unidirectional, flowing from the memory controller to the memories themselves.
This implies a certain amount of simplicity where the timing relationship between the clock and the control values is determined by a single chip in the system. Variation from chip to chip must be accounted for in system design, but timing in any one system is stable. Furthermore, unidirectional signals are easier to terminate electrically, providing cleaner signal swings to the receivers and to the logic analyzer.