During the early day's of microcomputing, system designers could achieve adequate performance using a relatively simple bus. These buses had a basic protocol with address, data, and control signals all present at the input when a clock edge arrived. While the bus watched for a target to respond, wait states were often added. But as processors became exponentially faster, buses became a cause for concern. Low bus bandwidth was causing extreme system bottlenecks.
Designers soon realized that there were a variety of ways to increase that bandwidth. Upping the number of signals on the data bus proved to be one simple way to do this. Today, growth in this area continues, but alternative methods to increase bandwidth have also been introduced. These practices include separating the location (address), intent (transaction type), and the relevant information (data). This separation allows for streaming data (bursting), reusing signal lines (multiplexing), and even overlapping transactions (pipelining). All of these techniques result in bus performance that has reasonably kept pace with advances in microprocessor technology.
Pipeline- and transaction-based buses are currently used in many common applications. In fact, nearly all computers have a variety of one or the other. The proliferation of bus architectures partially resulted from the separation of processor, I/O, graphics, and memory buses. The processor front-side bus (FSB), the PCI bus, and the accelerated graphics port (AGP) are just a few examples from a typical system (Fig. 1). Intel began utilizing advanced buses early in the x86 architecture, while Motorola's use of pipelined buses was evident in the PowerPC. Even ARM, the low-power newcomer, has implemented a pipeline in its processor-bus family. Though different, each of these buses contains the same basic transactional elements and pipelining architecture that present challenges to test equipment, such as a logic analyzer.
Advanced buses break bus action into different transactions.Early in the transfer, a transaction type identifies a device's intent using the bus. This foresight enables intelligent recipients to begin processing before an entire transfer is complete. In addition, the bus can be partitioned into discrete logical chunks or phases with a defined end phase. The definition of these elements becomes part of the fundamental bus architecture. The entire transfer of all phases is defined as the transaction (Fig. 2). Multiplexing, bursting, and pipelining all use transactions as a foundation.
A data write can explain how a Write Transaction evolves into a burst transfer. A sender begins by announcing its intent to do a write and giving a start location. After this setup, the sender begins inundating the receiver with data. Because the receiver has already acknowledged the start location, it then takes on the responsibility of tracking the continued destination of this data. This is typically done by incrementing an address counter on the word size. The bus is thereby emancipated from the tedious, yet important, task of providing a destination for every data transfer. Plus, overhead work is greatly reduced.
An example of a transaction-based bus that allows bursting is the PCI bus. After announcing the start location, or address, of a read or write, the data is sent continually across the bus. Control signals determine the start and end of the transfer, while the receiver of the information has the task of incrementing the address counter and placing the data in the proper location.
The P6 family of processors, which includes the Pentium II Xeon, Pentium II, and Pentium Pro processors, as well as the Intel Celeron and Mobile Pentium II, utilizes the P6 family system bus as a processor front-side bus. This architecture introduced an 8-stage pipeline, which allows for much higher utilization of the electrical traces on the motherboard. A deferred-reply transaction was added to the P6 family system-bus architecture, adding a new and highly desirable dimension to the bus. Many microprocessor vendors currently use different permutations of these bus-architecture elements in their processor FSBs.
Not only does the pipelining, or queuing, of actions allow a device to begin work on a transaction before it is complete, it actually lets another transaction begin before its predecessor is complete. This is physically accomplished by defining a certain group of signals that can be used only for a phase of each transaction. Once the phase is over, another device is free to use those signals. Because there is less latency between the beginning of different actions, there is higher bandwidth. In the P6 family system-bus architecture, the pipeline is tracked by devices on the bus using an in-order queue.
Deferred response, a very apt name, is simply the ability for any bus agent to say, "Hey, I'm not ready yet. Go do something else, and I'll get back to you when I've got what you asked for." This simple concept dramatically increases bus efficiency by not requiring the initiator to continually retry the request.
During the early day's of microcomputing, system designers could achieve adequate performance using a relatively simple bus. These buses had a basic protocol with address, data, and control signals all present at the input when a clock edge arrived. While the bus watched for a target to respond, wait states were often added. But as processors became exponentially faster, buses became a cause for concern. Low bus bandwidth was causing extreme system bottlenecks.
Designers soon realized that there were a variety of ways to increase that bandwidth. Upping the number of signals on the data bus proved to be one simple way to do this. Today, growth in this area continues, but alternative methods to increase bandwidth have also been introduced. These practices include separating the location (address), intent (transaction type), and the relevant information (data). This separation allows for streaming data (bursting), reusing signal lines (multiplexing), and even overlapping transactions (pipelining). All of these techniques result in bus performance that has reasonably kept pace with advances in microprocessor technology.
Pipeline- and transaction-based buses are currently used in many common applications. In fact, nearly all computers have a variety of one or the other. The proliferation of bus architectures partially resulted from the separation of processor, I/O, graphics, and memory buses. The processor front-side bus (FSB), the PCI bus, and the accelerated graphics port (AGP) are just a few examples from a typical system (Fig. 1). Intel began utilizing advanced buses early in the x86 architecture, while Motorola's use of pipelined buses was evident in the PowerPC. Even ARM, the low-power newcomer, has implemented a pipeline in its processor-bus family. Though different, each of these buses contains the same basic transactional elements and pipelining architecture that present challenges to test equipment, such as a logic analyzer.
Advanced buses break bus action into different transactions.Early in the transfer, a transaction type identifies a device's intent using the bus. This foresight enables intelligent recipients to begin processing before an entire transfer is complete. In addition, the bus can be partitioned into discrete logical chunks or phases with a defined end phase. The definition of these elements becomes part of the fundamental bus architecture. The entire transfer of all phases is defined as the transaction (Fig. 2). Multiplexing, bursting, and pipelining all use transactions as a foundation.
A data write can explain how a Write Transaction evolves into a burst transfer. A sender begins by announcing its intent to do a write and giving a start location. After this setup, the sender begins inundating the receiver with data. Because the receiver has already acknowledged the start location, it then takes on the responsibility of tracking the continued destination of this data. This is typically done by incrementing an address counter on the word size. The bus is thereby emancipated from the tedious, yet important, task of providing a destination for every data transfer. Plus, overhead work is greatly reduced.
An example of a transaction-based bus that allows bursting is the PCI bus. After announcing the start location, or address, of a read or write, the data is sent continually across the bus. Control signals determine the start and end of the transfer, while the receiver of the information has the task of incrementing the address counter and placing the data in the proper location.
The P6 family of processors, which includes the Pentium II Xeon, Pentium II, and Pentium Pro processors, as well as the Intel Celeron and Mobile Pentium II, utilizes the P6 family system bus as a processor front-side bus. This architecture introduced an 8-stage pipeline, which allows for much higher utilization of the electrical traces on the motherboard. A deferred-reply transaction was added to the P6 family system-bus architecture, adding a new and highly desirable dimension to the bus. Many microprocessor vendors currently use different permutations of these bus-architecture elements in their processor FSBs.
Not only does the pipelining, or queuing, of actions allow a device to begin work on a transaction before it is complete, it actually lets another transaction begin before its predecessor is complete. This is physically accomplished by defining a certain group of signals that can be used only for a phase of each transaction. Once the phase is over, another device is free to use those signals. Because there is less latency between the beginning of different actions, there is higher bandwidth. In the P6 family system-bus architecture, the pipeline is tracked by devices on the bus using an in-order queue.
Deferred response, a very apt name, is simply the ability for any bus agent to say, "Hey, I'm not ready yet. Go do something else, and I'll get back to you when I've got what you asked for." This simple concept dramatically increases bus efficiency by not requiring the initiator to continually retry the request.