As System-On-A-Chip complexity increases, testing the millions of gates that get integrated on the chip has become an ever more challenging and more expensive task. On-chip test support logic and built-in self-test (BIST) circuits have been developed to handle the design-for-test (DFT) methodologies that are now almost mandatory for new designs. Such test capabilities are needed because many functions embedded in the complex chips are unreachable from external pins, or because the time and cost of the test systems to access the blocks makes the testing very slow and very expensive.
Typically, when the first system-on-a-chip (SoC) comes off the manufacturing line, extensive testing is performed to ensure that the DFT circuits function as desired. But the multimillion dollar test systems that are often required to perform the analysis are usually kept very busy on the production test floor. Finding time to perform engineering verification frequently means staying overnight at the factory to get some time on the large production tester. On top of that, these "big iron" test systems aren't optimized to handle the internal test structures inside the SoCs.
A fresh approach to address these issues is a compact, low-cost system, the Validator 500. Developed by Teseda Corp., the system allows verification of the DFT structures in the SoCs. By validating that the DFT structures are correct, the system guarantees that the SoC's testability features are correct. That will result in high-quality tests that effectively reject faulty products. The system can be used by design engineers, a DFT specialist, a product engineer, or anyone else who has the responsibility of making sure that either the chip's DFT is working properly, or the DFT tests are correct, or both.
If the cores employed on the chip weren't fully DFT-enabled, the ASIC designers could leverage work done by the IEEE P1500 committee, which is currently developing a standard for embedded core test (SECT). The standard will define a sort of wrapper that helps isolate the core and permits the system to test it (see "P1500: The Standard For Embedded Test,").
The Teseda solution is a small desktop unit. It's the first of a family of DFT-focused test systems that enable engineering validation and circuit de- bugging at a cost of about $60,000 per test system plus the appropriate wafer probe or test adapter. The Validator 500 focuses on dc-scan testing and can reduce the cost of testing early prototypes by 70× compared to the large automated-test-equipment (ATE) systems. Teseda plans to introduce additional test options that will allow validation of ac scan, IDDQ, and additional support for BIST and boundary-scan validation.
These versions will allow designers to perform failure analysis and characterization. Furthermore, the ability to loop-back failure information to an ATPG for fault isolation and analysis is rapid and painless because the system naturally provides information in a format familiar to the ATPG. The system will also find use in manufacturing test and wafer sorting.
To clarify what the Validator 500 does, it exercises the on-chip test circuits. Through the use of test programs and data streams, it can verify that the test structures on the chip are working and are connected according to the specifications. In other words, it lets engineers debug DFT test data and circuit structures.
When the test patterns are run, the tools will let users determine the general location or conditions of a problem and make online changes to further isolate the problem. The software is called DFT-intelligent because it preserves the structural information supplied by the design automation tools and evaluates whether or not the DFT is operating correctly.
For example, the DFT tools can help identify errors that are almost obscured on traditional ATE systems. Consider a test with failures detected on cycle #579, #10,253, and #299,021. On a "flat" machine, these failures can appear random and unrelated. But on a DFT-focused system that knows the structure of the DFT tests and can reconstitute them, relating the failures to the logic can show a link. These failures could perhaps have been shown to originate in the same register in a particular core on the chip during three separate scan tests. The ability of the software tools to navigate back and forth between the hierarchical design view and the flat view makes it easier to spot links between errors.
The Validator doesn't perform functional testing of the blocks. That task remains in the domain of the larger ATE systems. However, by evaluating the DFT structures and data early in the validation process through a low-cost system that you can keep on your lab bench, you can find logic bugs or errors that would waste the valuable time of the large ATE systems.
To accomplish its job, the Validator simplifies and speeds the test preparation by directly importing automatic test-pattern generation (ATPG) scan test data in IEEE 1450 (STIL) format. The files include vector data and DFT structural descriptions. When performing the DFT evaluation, the Validator can check out devices with as many as 128 internal scan chains and four clock domains. Data can be clocked through the chip at a maximum rate of 50 MHz, and a maximum of 32 million pattern vectors can be validated at a time. The system can also generate a million BIST clock pulses with a single tester vector.