The Benefits—And Hazards—Of Scan Compression

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By reducing the amount of data needed to thoroughly test digital circuits, compression frees up enough tester memory to add tests (e.g., transition delay pattern sets) that further improve quality. Because off-the-shelf tools have become increasingly automated and easier to use, semiconductor firms are rapidly embracing scan compression to lower costs at the tester.

It's because scan compression has proven so successful in reducing test costs that designers and managers alike often maintain, mistakenly, that more is better. Although it's reasonable to assume that ever-higher levels of compression will achieve ever-higher cost savings, the economics underlying the technology suggest otherwise. In fact, compression without limits increases costs.

In this article, we'll see why this is the case by exploring how compression reduces test time and what factors degrade compression performance and cost savings. We'll determine what level of savings designers can realistically expect and how to maximize these savings. In the process, we'll arrive at some practical implementation guidelines that will help designers reap the benefits of scan compression while avoiding its hazards.

Test Execution Cost and Test Time Reduction
Assume that a design with F scan flops has C scan chains of equal depth, each connected to a pair of dedicated scan I/O pins. Then without scan compression, the chain depth is F/C and we can approximate the cost C_T of testing each yielding device on the tester as:

R is the tester cost ($/sec), P_B the number of basic scan ATPG patterns, Y₀ the manufacturing yield, and f the tester scan shift frequency. The multiplier α reflects a slight decrease on average in test time due to failing die (Y₀≤ α ≤ 1)¹.  C_T is referred to as the test execution cost. 

Test application time reduction (TATR) is accomplished by increasing the number of scan chains by a factor of "x" so that the depth of each chain is reduced by the same factor. The variable "x" is loosely referred to as the amount of compression, but it's actually the compression ratio, the number of internal scan chains divided by the number of scan channels, C. 

For example, if your design has C = 10 scan channels, then implementing x = 20 compression creates 20 X 10 = 200 chains 1/20th the size of the original depth.  Compression and decompression circuits between the chain I/Os and the scan I/O pins ensure that the number of scan I/O pins remains the same. Sharing of internal inputs to the scan chains means that the number of bits in each scan ATPG pattern is reduced by the same factor, x.  Likewise, reducing scan depth by the same factor makes it possible to scan in and test x times more patterns in the same amount of time. 

The cost savings ΔCost from TATR is the difference in test execution costs between basic scan and scan compression:

 

Dividing by C_T gives the percentage cost reduction: 1 — 1/x.  Cost savings garnered by Equation 2 are ideal because the formula doesn't account for various negating effects that offset savings. Let's now examine each of these effects in turn, using a 65-nm design consisting of 97.1 million gates, 1.3 million scan flops, and 10 scan channels for the examples. For this article we've adjusted measurements of tool-specific behavior in order to highlight the described phenomena.

Pattern Inflation
As the compression ratio increases, more patterns are needed to maintain the same high fault coverage. Pattern inflation from compression is always present to some degree, although the use of multiple clock domains in today's systems-on-a-chip tends to increase pattern inflation. That's because it increases the level of unknown logic values propagating through the circuits. To compensate, commercial compression tools employ various methods, including X-blocking, to ensure relatively low and linear pattern inflation over a wide range of compression levels.

The number of patterns generated for a scan-compressed design P'(x) is a function of the basic scan ATPG pattern count P_B and the pattern inflation rate ε, which is the percentage increase in pattern count per unit increase in the compression ratio x:²

 

From a cost-savings perspective, the pattern inflation rate itself has only a minor impact as long as it remains linear in x.  This is because differences in compressed test times for different inflation rates are insignificant compared with the test times using basic scan.  To illustrate, the black curves in Figure 1 display tester cycle count for zero pattern inflation and ε = 4%, an extraordinarily high pattern inflation rate.

Further impact on savings can result if there's a pronounced step increase in pattern count relative to P_B for any compression level x, such that the pattern count in Equation 3 is instead described by:

The step increase is illustrated in Figure 2, wherein the red line, representing P'(x) in Equation 4, is the least-squares fit of different compression data points. The basic scan pattern count is P_B = 1100, whereas the y-intercept of the line is nearly 50% greater:

 

The blue curves in Figure 1 show the tester cycle count for e = 0% and e = 4%, assuming the step increase of Figure 2.