The Benefits—And Hazards—Of Scan Compression

Scenario 2 takes into consideration pattern inflation, which tends to pull the cost curve downward. Most of this difference is due to a 60% step increase in pattern count from PB that is common across all compression levels (the cost difference between zero and 0.42% pattern inflation rate is too negligible to be displayed separately on the graph).

Scenario 3 accounts for non-zero compression area overhead. Savings from test time reduction are offset by the silicon-area overhead cost of compression. An optimal compression level occurs at x = 32, at which the incremental increase in silicon cost is equal to the incremental decrease in test execution cost. Above this level, silicon cost increases at a faster rate than the decrease in execution cost; net savings decline precipitously with higher compression until a break-even point is reached at x = 196, above which compression actually increases costs.

Scenario 4 takes all of the negating factors into account by highlighting the cost impact of decreasing yield due to compression. The break-even point shifts down to x = 174, while the optimal compression level decreases slightly to x = 29, where cost savings reaches the maximum level of 86%.

Conclusion:  Steps to Maximize Savings
The preceding analysis indicates that real cost savings from scan compression are substantial, though less than the ideal levels usually claimed by the marketers of compression tools. You should expect typical savings from test time reduction in the 80% to 95% range, depending on die size, manufacturing yield, tester scan shift frequency, tester cost, cost of silicon, and the compression cost variables, which are both design- and tool-dependent. You can maximize savings by following these guidelines when implementing scan compression in your designs:

1. Utilize as many I/O pins as feasible while avoiding very high compression levels.

Increasing the number of scan chains from C1 to C2in the uncompressed design reduces the chain depth and requires less compression to reduce test time to a given level. The amount of compression needed to achieve the same test time is reduced by approximately 1 – C1/C2. For example, if your design utilizes 100 scan channels instead of 10, then the compression ratio needed to achieve the same test time is reduced by 90%. This is advantageous at nominal compression levels, but keep in mind a very large number of chains at high levels could increase routing congestion.

2. Select a compression ratio in the range of the optimal compression level.

Regardless of the number of scan channels, cost savings start to plateau—even under ideal assumptions—by x = 20. Maximum savings occur at a level higher or lower than this, depending on the compression cost variables. Use the cost-savings formula in Equation 7 to estimate the optimal compression level for your design.

3. Minimize the number of unknown logic states.

Although it may not be possible to produce an "X-clean" design, there are ways to reduce the amount of unknowns during scan testing. Timing exceptions associated with multiple internal clocks that aren't skew-balanced are a leading culprit of unknown logic states. The problem often occurs when using a single external clock (or single internal clock controller) to control many internal clock domains. A better approach is to employ different on-chip clock controllers to generate separate capture clocks (one for each clock domain), thereby using the skew-balanced clock trees in test mode. Although there will be an area penalty associated with the additional clock controllers, no increase in routing congestion should occur.

Another way to reduce unknowns is to resolve all internal tri-state buses to known values in test mode. Finally, consider bypassing all embedded memories during stuck-at testing. For transition delay tests, techniques to propagate known memory states are possible though more involved to implement.

4. Minimize wire routing congestion from scan chain interconnect.

Embedding the compression logic inside the design's physical hierarchy can reduce routing congestion. To illustrate, Figure 6 shows two large physical partitions, A and B, each containing its own compression circuits. Smaller cores C and D connect with compression circuits at the top level, along with other top-level logic. Embedding compression in the largest physical blocks decreases routing at the top level; most connectivity is confined to the interior of the blocks, and this reduces the length of wires that connect the compression logic to the scan chain I/Os. To maintain compression performance, it's essential that all scan chains have approximately the same depth. 

5. Anticipate your toughest design challenges and select implementation tools accordingly.

Perhaps the most important cost not factored in by the equations concerns implementation cost—the engineering time and effort required to implement compression. After all, reducing test time isn't very cost effective if it adds weeks to your design cycle and delays your tape-out. To manage implementation cost, it might be best to invest in EDA solutions such as Synopsys' Galaxy Design Platform for Test, which have a high degree of predictability and correlation. Predictability reflects the extent to which your compression performance goals are achieved by the tool.4 Correlation considers the impact of compression on area, timing, power, and routability. Correlation reflects self-consistency of the design platform as a front-to-back implementation flow. Thus, results you achieve at the logical level are observed in silicon, with a minimal amount of effort. 

We hope these guidelines, while by no means exhaustive, will help you maximize savings from compression.

References

1. S. Wei, P.K. Nag, R.D. Blanton, A. Gattiker and W. Maly, "To DFT or Not to DFT?" Proc. Int'l Test Conf., 1997, Paper 23.3.

2. C. Allsup, "The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time," Proc. Int'l Test Conf., Lecture 2.2, 2006.

3. T.M Michalka, R.C. Varshney, J.D. Meindl, "A Discussion of Yield Modeling with Defect Clustering, Circuit Repair, and Circuit Redundancy," IEEE Transactions on Semiconductor Manufacturing, Vol. 3, No. 3, Aug. 1990, Pages: 116-127.

4. C. Allsup, "Measuring Scan Compression Performance," appearing in EDA DesignLine (www.edadesignline.com), May 2007.