WELCOME TO EMBEDDED INSTRUMENTATION
As semiconductor feature sizes continue to shrink into the 65-nm and below range, chip density and complexity continue to increase as vendors load more onto a single chip. These smaller geometries also permit higher data rates well into the 5-GHz+ region. What’s resulted is even more difficulties
in testing these chips and the boards they populate.
This problem has forced chip vendors to go beyond scan chains and JTAG to create innovative techniques to access and test the circuitry on these advanced chips. Some are proprietary to chip vendors, and some can be used in conjunction with JTAG. Collectively, these techniques are known as embedded instrumentation.
This testing problem is especially acute with the newer high-speed serial buses being deployed in most new computers and other equipment. PCI Express, Fibre Channel, 10-Gbit/s Ethernet, Serial ATA (SATA), fully buffered DIMM (FBD), and others are examples.
Considerable distortion and signal degradation
occurs at speeds of 5 Gbits/s and above, even over several inches of PCB trace, making it difficult to really know what the signal looks like. Connecting a scope to such a trace even introduces further distortion.
Since such traditional methods are no longer as useful, new embedded testing methods are on the drawing board.
This plan moves some or all of the testing instrument or circuit on-chip. Embedded instrumentation is an extension
of BIST. It can generally be defined as any design validation, test, or debug IP embedded in a core, SoC, system-in-a-package (SiP), board, or system that can be used by design, test, or manufacturing to achieve testing, measuring, or other engineering
tasks.
Because embedded instrumentation is in its infancy, there are no standards. But the IEEE 1149.1 JTAG group proposed an extension to the boundary-scan standard that will allow the JTAG TAP to manage the configuration, operation, and collection of data from this embedded instrumentation
circuitry. This effort falls under the aegis of IEEE 1687, or IJTAG, too.
“When you start to scratch the surface, you see that embedded instrumentation is critical as the industry moves forward to higher speeds, smaller geometries, and greater densities,” says Glenn Woppman, president and CEO of ASSET InterTech.
“Not everyone calls it embedded instrumentation, but much of the logic that is being embedded addresses issues like design validation, test, debug, device, and board monitoring and other types of instrumentation functionality. That is what we call embedded instrumentation,” adds Woppman.
ASSET is so confident in embedded instrumentation that it has repositioned itself as a company devoted to providing open tools for embedded instrumentation.
Its new motto is “Driving Embedded Instrumentation” (Fig. 6).
When you come down to it, embedded instrumentation could be considered the next evolution of the test and measurement industry. It is a generational step beyond virtual instrumentation and its modular
hardware and software like National Instruments’ LabVIEW. ASSET InterTech’s
ScanWorks JTAG software platform
appears to be a great starting point for becoming the LabVIEW of embedded instrumentation.
Intel’s IBIST (Interconnect Built In Self Test) design validation and test architecture
allows chip-to-chip interconnect testing
and design validation of high-speed buses on a PCB. It’s built into Intel’s 5300 and 7300 series Quad-Core Xeon processor-
based platforms used in servers. It will also be used in Intel’s next-generation Nehalem processor platforms.
IBIST uses signal-integrity analysis through margining, bit-error-rate testing
(BERT), and pattern generation testing.
It also uses boundary-scan test, in-system programming, and design for test. ASSET’s ScanWorks supports it.
Lots of other companies are also beginning to incorporate embedded instrumentation. For example, Altera is making its Pre-emphasis and Equalization
Link Estimator (PELE) available to electronic design automation (EDA) companies
like Mentor so designers can use it for signal-integrity measurements on the Stratix II GX FPGAs. DAFCA, an EDA company, allows chip designers to incorporate
reconfigurable instrumentation from its IP library.
Logic Vision lets designers deploy its embedded serializer-deserializer (SERDES) loop-back solution, which characterizes the parameters that determine
signal eye distortion. Maxim incorporates
monitoring instruments in some of its power-management chips. And, Rambus
is integrating a programmable pseudo-random-pattern-generating instrument and bit-stream comparators into I/O blocks on its memory chips.
Synopsys now offers its DesignWare Verification Library of embedded instrumentation
IP. Vitesse Semiconductor has come up with a series of new transceiver and SERDES chips that incorporate its VScope waveform-viewing technology based on equalization and a unique sampling
technique. Furthermore, Xilinx’s ChipScope Pro real-time debug and verification
tool inserts a logic analyzer, bus analyzer,
and virtual I/O instruments directly into an FPGA. Expect more news and announcements in this space in the coming
months.
REFERENCE
Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, editors, System-On-Chip Test Architectures, Nanometer Design for Testability, Morgan Kaufmann Publishers,
2008.